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| author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 22:09:57 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-15 19:18:34 -0500 |
| commit | 1368b914e93a3af332f787d3d41c106d11bb90da (patch) | |
| tree | 9893ccae5d2d8cbf2ce855e09d6b8f30b56a21bc /sim/testsuite/sh/pshlr.s | |
| parent | e403a898b5893337baea73bcb001ece74042f351 (diff) | |
| download | gdb-1368b914e93a3af332f787d3d41c106d11bb90da.zip gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.gz gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.bz2 | |
sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.
We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim". Since we have no
other dirs in this tree, and no plans to add any, should be fine.
Diffstat (limited to 'sim/testsuite/sh/pshlr.s')
| -rw-r--r-- | sim/testsuite/sh/pshlr.s | 152 |
1 files changed, 152 insertions, 0 deletions
diff --git a/sim/testsuite/sh/pshlr.s b/sim/testsuite/sh/pshlr.s new file mode 100644 index 0000000..36cb47f --- /dev/null +++ b/sim/testsuite/sh/pshlr.s @@ -0,0 +1,152 @@ +# sh testcase for pshl <reg> +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pshl_reg: ! shift arithmetic, register operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x10000, x0 + set_sreg 0x0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x10000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x20000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x30000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x40000, y0 + pshl x0, y0, x0 + assert_sreg 0x100000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x50000, y0 + pshl x0, y0, x0 + assert_sreg 0x200000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x60000, y0 + pshl x0, y0, x0 + assert_sreg 0x400000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x70000, y0 + pshl x0, y0, x0 + assert_sreg 0x800000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x80000, y0 + pshl x0, y0, x0 + assert_sreg 0x1000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x90000, y0 + pshl x0, y0, x0 + assert_sreg 0x2000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xa0000, y0 + pshl x0, y0, x0 + assert_sreg 0x4000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xb0000, y0 + pshl x0, y0, x0 + assert_sreg 0x8000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xc0000, y0 + pshl x0, y0, x0 + assert_sreg 0x10000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xd0000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xe0000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xf0000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x100000, y0 + pshl x0, y0, x0 + assert_sreg 0x00000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x0, x0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + |