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| author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 22:09:57 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-15 19:18:34 -0500 |
| commit | 1368b914e93a3af332f787d3d41c106d11bb90da (patch) | |
| tree | 9893ccae5d2d8cbf2ce855e09d6b8f30b56a21bc /sim/testsuite/sh/fsub.s | |
| parent | e403a898b5893337baea73bcb001ece74042f351 (diff) | |
| download | gdb-1368b914e93a3af332f787d3d41c106d11bb90da.zip gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.gz gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.bz2 | |
sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.
We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim". Since we have no
other dirs in this tree, and no plans to add any, should be fine.
Diffstat (limited to 'sim/testsuite/sh/fsub.s')
| -rw-r--r-- | sim/testsuite/sh/fsub.s | 136 |
1 files changed, 136 insertions, 0 deletions
diff --git a/sim/testsuite/sh/fsub.s b/sim/testsuite/sh/fsub.s new file mode 100644 index 0000000..dfe9172 --- /dev/null +++ b/sim/testsuite/sh/fsub.s @@ -0,0 +1,136 @@ +# sh testcase for fsub +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsub_single: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bt .L0 + fail +.L0: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi1 fr2 + fcmp/eq fr1, fr2 + bt .L1 + fail +.L1: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bt .L2 + fail +.L2: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi1 fr2 + fneg fr2 + fcmp/eq fr1, fr2 + bt .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i -1, fr1 + assert_fpreg_i -1, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fsub_double: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi0 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L10 + fail +.L10: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi1 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L11 + fail +.L11: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi0 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L12 + fail +.L12: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi1 fr4 + single_prec + fneg fr4 + double_prec + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 1, dr0 + assert_dpreg_i -1, dr2 + assert_dpreg_i -1, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 |