sim: testsuite: flatten tree

Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.

We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim".  Since we have no
other dirs in this tree, and no plans to add any, should be fine.

1 files changed, 109 insertions, 0 deletions

diff --git a/sim/testsuite/m32r/trap.cgs b/sim/testsuite/m32r/trap.cgs
new file mode 100644
index 0000000..59e136a
--- /dev/null
+++ b/sim/testsuite/m32r/trap.cgs
@@ -0,0 +1,109 @@
+# m32r testcase for trap #$uimm4
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global trap
+trap:
+
+; Test 1: bbpsw = 0, bpsw = 1, psw = 0
+
+	; bbsm = 0, bie = 0, bbcond = 0
+	mvi_h_gr r4, 0
+	mvtc r4, cr8
+
+	; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0
+	mvi_h_gr r4, 0xc100
+	mvtc r4, cr0
+
+	; bbpc = 0
+	mvaddr_h_gr r4, 0
+	mvtc r4, bbpc
+
+	; bpc = 42
+	mvaddr_h_gr r4, 42
+	mvtc r4, bpc
+
+	; Copy trap2_handler to trap area of memory.
+	ld24 r0,#0x48 ; address of trap 2 handler
+	ld24 r1,#trap2_handler
+	ld r2,@r1
+	st r2,@r0
+	; Set up return address.
+	ld24 r5,#trap2_ret1
+
+trap_insn1:
+	trap #2
+	fail
+
+trap2_ret1:
+	; test bbsm = 1, bbie = 1, bbcond = 1
+	mvfc r4, cr8
+	test_h_gr r4, 0xc1
+
+	; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0
+	mvfc r4, cr0
+	test_h_gr r4, 0
+
+	; test bbpc = 42
+	mvfc r4, bbpc
+	test_h_gr r4, 42
+
+	; test bpc = proper return address
+	mvfc r4, bpc
+	test_h_gr r4, trap_insn1 + 4
+
+; Test 2: bbpsw = 1, bpsw = 0, psw = 1
+
+	; bbsm = 1, bie = 1, bbcond = 1
+	mvi_h_gr r4, 0xc1
+	mvtc r4, cr8
+
+	; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1
+	mvi_h_gr r4, 0xc1
+	mvtc r4, cr0
+
+	; bbpc = 42
+	mvaddr_h_gr r4, 42
+	mvtc r4, bbpc
+
+	; bpc = 0
+	mvaddr_h_gr r4, 0
+	mvtc r4, bpc
+
+	; Set up return address.
+	ld24 r5,#trap2_ret2
+
+trap_insn2:
+	trap #2
+	fail
+
+trap2_ret2:
+	; test bbsm = 0, bbie = 0, bbcond = 0
+	mvfc r4, cr8
+	test_h_gr r4, 0
+
+	; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0
+	mvfc r4, cr0
+	test_h_gr r4, 0xc180
+
+	; test bbpc = 0
+	mvfc r4, bbpc
+	test_h_gr r4, 0
+
+	; test bpc = proper return address
+	mvfc r4, bpc
+	test_h_gr r4, trap_insn2 + 4
+
+	pass
+
+	.data
+
+; Don't use rte as it will undo the effects of trap we're testing.
+
+	.p2align 2
+trap2_handler:
+	jmp r5
+	nop