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author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 22:09:57 -0500 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-15 19:18:34 -0500 |
commit | 1368b914e93a3af332f787d3d41c106d11bb90da (patch) | |
tree | 9893ccae5d2d8cbf2ce855e09d6b8f30b56a21bc /sim/testsuite/m32r/rte.cgs | |
parent | e403a898b5893337baea73bcb001ece74042f351 (diff) | |
download | gdb-1368b914e93a3af332f787d3d41c106d11bb90da.zip gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.gz gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.bz2 |
sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.
We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim". Since we have no
other dirs in this tree, and no plans to add any, should be fine.
Diffstat (limited to 'sim/testsuite/m32r/rte.cgs')
-rw-r--r-- | sim/testsuite/m32r/rte.cgs | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/sim/testsuite/m32r/rte.cgs b/sim/testsuite/m32r/rte.cgs new file mode 100644 index 0000000..b389fe1 --- /dev/null +++ b/sim/testsuite/m32r/rte.cgs @@ -0,0 +1,87 @@ +# m32r testcase for rte +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rte +rte: + +; Test 1: bbpsw = 0, bpsw = 1, psw = 0 + + ; bbsm = 0, bie = 0, bbcond = 0 + mvi_h_gr r4, 0 + mvtc r4, cr8 + + ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvi_h_gr r4, 0xc100 + mvtc r4, cr0 + + ; bbpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bbpc + + ; bpc = ret1 + mvaddr_h_gr r4, ret1 + mvtc r4, bpc + + rte + fail + +ret1: + ; test bbsm = 0, bbie = 0, bbcond = 0 + mvfc r4, cr8 + test_h_gr r4, 0 + + ; test bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvfc r4, cr0 + test_h_gr r4, 0xc1 + + ; test bbpc = 0 + mvfc r4, bbpc + test_h_gr r4, 0 + + ; test bpc = 0 + mvfc r4, bpc + test_h_gr r4, 0 + +; Test 2: bbpsw = 1, bpsw = 0, psw = 1 + + ; bbsm = 1, bie = 1, bbcond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr8 + + ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr0 + + ; bbpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bbpc + + ; bpc = ret2 + 2 + mvaddr_h_gr r4, ret2 + 2 + mvtc r4, bpc + + rte + fail + +ret2: + ; test bbsm = 1, bbie = 1, bbcond = 1 + mvfc r4, cr8 + test_h_gr r4, 0xc1 + + ; test bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0xc100 + + ; test bbpc = 42 + mvfc r4, bbpc + test_h_gr r4, 42 + + ; test bpc = 42 + mvfc r4, bpc + test_h_gr r4, 42 + + pass |