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| author | Jim Wilson <jimw@sifive.com> | 2021-04-07 18:51:52 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2021-04-07 18:51:52 -0700 |
| commit | 0592e80bcf1bbab2fbbb110ea395f9608e4f594c (patch) | |
| tree | b175364127540032ba3a64ca889ab5d67efa82ea /sim/testsuite/iq2000/ChangeLog | |
| parent | bf5271659d0d78174041aa0e198406c9ecacc7a4 (diff) | |
| download | gdb-0592e80bcf1bbab2fbbb110ea395f9608e4f594c.zip gdb-0592e80bcf1bbab2fbbb110ea395f9608e4f594c.tar.gz gdb-0592e80bcf1bbab2fbbb110ea395f9608e4f594c.tar.bz2 | |
Aarch64 sim fix for gcc-10 miscompilation.
This fixes a problem that occurs when compiled by gcc-10, as the code
is relying on undefined overflow behavior. This is fixed by replacing
compares between 32-bit and 64-bit results with compares that just use
the 64-bit results with a cast.
PR sim/27483
* simulator.c (set_flags_for_add32): Compare uresult against
itself. Compare sresult against itself.
Diffstat (limited to 'sim/testsuite/iq2000/ChangeLog')
0 files changed, 0 insertions, 0 deletions