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| author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 22:09:57 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-15 19:18:34 -0500 |
| commit | 1368b914e93a3af332f787d3d41c106d11bb90da (patch) | |
| tree | 9893ccae5d2d8cbf2ce855e09d6b8f30b56a21bc /sim/testsuite/bfin/cc5.S | |
| parent | e403a898b5893337baea73bcb001ece74042f351 (diff) | |
| download | gdb-1368b914e93a3af332f787d3d41c106d11bb90da.zip gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.gz gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.bz2 | |
sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.
We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim". Since we have no
other dirs in this tree, and no plans to add any, should be fine.
Diffstat (limited to 'sim/testsuite/bfin/cc5.S')
| -rw-r--r-- | sim/testsuite/bfin/cc5.S | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/sim/testsuite/bfin/cc5.S b/sim/testsuite/bfin/cc5.S new file mode 100644 index 0000000..593b3bd --- /dev/null +++ b/sim/testsuite/bfin/cc5.S @@ -0,0 +1,90 @@ +// ALU test program. +// Test instructions reg = (A0+=A1) + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + loadsym P0, data0; + + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// add accums and transfer result + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R6 = ( A0 += A1 ); + CHECKREG R6, 0x22222222; + R6 = A0.w; + CHECKREG R6, 0x22222222; + R7 = A0.x; + CHECKREG R7, 0; + R6 = A1.w; + CHECKREG R6, 0x11111111; + R7 = A1.x; + CHECKREG R7, 0; + +// add accums and transfer result (saturate positive) + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R6 = ( A0 += A1 ); + CHECKREG R6, 0x7fffffff; + R6 = A0.w; + CHECKREG R6, 0xfffffffe; + R7 = A0.x; + CHECKREG R7, 0; + R6 = A1.w; + CHECKREG R6, 0x7fffffff; + _DBG ASTAT; + R7 = A1.x; + _DBG ASTAT; + CHECKREG R7, 0; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY); + +// add accums and transfer result (saturate negative) + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + A1.x = R3.L; + A0.x = R3.L; + R6 = ( A0 += A1 ); + CHECKREG R6, 0x80000000; + R6 = A0.w; + CHECKREG R6, 0x00000000; + R7 = A0.x; + CHECKREG R6, 0; + R6 = A1.w; + CHECKREG R6, 0x80000000; + R7 = A1.x; + CHECKREG R7, 0xffffffff; + R7 = ASTAT; + _DBG ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); + + pass + + .data +data0: + .dw 0x1111 + .dw 0x1111 + .dw 0xffff + .dw 0x7fff + .dw 0x0000 + .dw 0x8000 + .dw 0x00ff + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 |