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| author | Michael Snyder <msnyder@vmware.com> | 2003-07-23 21:17:33 +0000 |
|---|---|---|
| committer | Michael Snyder <msnyder@vmware.com> | 2003-07-23 21:17:33 +0000 |
| commit | 9e1d0fc1a1f904291ab6b1445a21530b3d2edbec (patch) | |
| tree | d05a4b3fe02d772b7a035c111b5f4679a0967015 /sim/sh | |
| parent | 15dee5d56138cdd48dc3f6b8c8e1d610b0131aa1 (diff) | |
| download | gdb-9e1d0fc1a1f904291ab6b1445a21530b3d2edbec.zip gdb-9e1d0fc1a1f904291ab6b1445a21530b3d2edbec.tar.gz gdb-9e1d0fc1a1f904291ab6b1445a21530b3d2edbec.tar.bz2 | |
2003-06-27 Michael Snyder <msnyder@redhat.com>
* gencode.c (op movsxy_tab): Fix an error in the bit pattern.
Diffstat (limited to 'sim/sh')
| -rw-r--r-- | sim/sh/ChangeLog | 1 | ||||
| -rw-r--r-- | sim/sh/gencode.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog index 0cd05f5..ad4bd8f 100644 --- a/sim/sh/ChangeLog +++ b/sim/sh/ChangeLog @@ -4,6 +4,7 @@ 2003-06-27 Michael Snyder <msnyder@redhat.com> + * gencode.c (op movsxy_tab): Fix an error in the bit pattern. * gencode.c (gensim_caselist): The movy instructions use registers R6 and R7 (not R4 and R5 like the movx insns). diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c index e5dee8f..e8e780f 100644 --- a/sim/sh/gencode.c +++ b/sim/sh/gencode.c @@ -1259,7 +1259,7 @@ op movsxy_tab[] = "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;", "iword &= 0xfd53; goto top;", }, - { "n", "n8","movx.w <DSP_Aa>,@<REG_x>+REG_8","111100xxaa101000", + { "n", "n8","movx.w <DSP_Aa>,@<REG_x>+REG_8","111100xxaa101100", "WWAT (R[n], DSP_R (m) >> 16);", "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];", "iword &= 0xfd53; goto top;", |