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authorMichael Snyder <msnyder@vmware.com>2003-07-23 21:14:54 +0000
committerMichael Snyder <msnyder@vmware.com>2003-07-23 21:14:54 +0000
commit15dee5d56138cdd48dc3f6b8c8e1d610b0131aa1 (patch)
tree5c6d43daeadf930fac0963120a25ba53ab6dfea9 /sim/sh
parent586b12adb4bd060c91a398806bf1ce17f6ef09df (diff)
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2003-06-27 Michael Snyder <msnyder@redhat.com>
* gencode.c (gensim_caselist): The movy instructions use registers R6 and R7 (not R4 and R5 like the movx insns).
Diffstat (limited to 'sim/sh')
-rw-r--r--sim/sh/ChangeLog5
-rw-r--r--sim/sh/gencode.c2
2 files changed, 6 insertions, 1 deletions
diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog
index d069a81..0cd05f5 100644
--- a/sim/sh/ChangeLog
+++ b/sim/sh/ChangeLog
@@ -4,6 +4,11 @@
2003-06-27 Michael Snyder <msnyder@redhat.com>
+ * gencode.c (gensim_caselist): The movy instructions use
+ registers R6 and R7 (not R4 and R5 like the movx insns).
+
+2003-06-27 Michael Snyder <msnyder@redhat.com>
+
* gencode.c (op movsxy_tab): Fix up some copy/paste errors
in name: s/REG_x/REG_y/.
diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c
index a0f8b59..e5dee8f 100644
--- a/sim/sh/gencode.c
+++ b/sim/sh/gencode.c
@@ -2159,7 +2159,7 @@ gensim_caselist (p)
s += 2;
break;
case 'y':
- printf (" int n = ((iword >> 8) & 1) + 4;\n");
+ printf (" int n = ((iword >> 8) & 1) + 6;\n");
needn = 1;
s += 2;
break;