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| author | David Edelsohn <dje.gcc@gmail.com> | 1997-04-24 00:56:33 +0000 |
|---|---|---|
| committer | David Edelsohn <dje.gcc@gmail.com> | 1997-04-24 00:56:33 +0000 |
| commit | 73da4db5873e6c759c2a755a8eaebb94b49a0f86 (patch) | |
| tree | d9636803e66eb64d443bb7f82679837fd47ec05f /sim/sh | |
| parent | 3be0e2289675a3cd99fa0c9ae7fea0b4d60e925c (diff) | |
| download | gdb-73da4db5873e6c759c2a755a8eaebb94b49a0f86.zip gdb-73da4db5873e6c759c2a755a8eaebb94b49a0f86.tar.gz gdb-73da4db5873e6c759c2a755a8eaebb94b49a0f86.tar.bz2 | |
* tconfig.in: New file.
* interp.c (sim_open): Handle missing arg to -E.
Diffstat (limited to 'sim/sh')
| -rw-r--r-- | sim/sh/.Sanitize | 1 | ||||
| -rw-r--r-- | sim/sh/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/sh/tconfig.in | 17 |
3 files changed, 23 insertions, 0 deletions
diff --git a/sim/sh/.Sanitize b/sim/sh/.Sanitize index 4b62874..0c6c23f 100644 --- a/sim/sh/.Sanitize +++ b/sim/sh/.Sanitize @@ -33,6 +33,7 @@ configure.in interp.c gencode.c syscall.h +tconfig.in Things-to-lose: diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog index c83d7f6..dd0444f 100644 --- a/sim/sh/ChangeLog +++ b/sim/sh/ChangeLog @@ -1,3 +1,8 @@ +Wed Apr 23 17:55:22 1997 Doug Evans <dje@canuck.cygnus.com> + + * tconfig.in: New file. + * interp.c (sim_open): Handle missing arg to -E. + Tue Apr 22 08:55:35 1997 Stu Grossman (grossman@critters.cygnus.com) * Makefile.in: Add clean targets. diff --git a/sim/sh/tconfig.in b/sim/sh/tconfig.in new file mode 100644 index 0000000..c5ec4fa --- /dev/null +++ b/sim/sh/tconfig.in @@ -0,0 +1,17 @@ +/* sh target config file */ + +/* Define this if the simulator supports profiling. + See the mips simulator for an example. + This enables the `-p foo' and `-s bar' options. + The target is required to provide sim_set_profile{,_size}. */ +/* #define SIM_HAVE_PROFILE */ + +/* Define this if the simulator uses an instruction cache. + See the h8/300 simulator for an example. + This enables the `-c size' option to set the size of the cache. + The target is required to provide sim_set_simcache_size. */ +/* #define SIM_HAVE_SIMCACHE */ + +/* Define this if the target cpu is bi-endian + and the simulator supports it. */ +#define SIM_HAVE_BIENDIAN |