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| author | Stu Grossman <grossman@cygnus> | 1995-11-15 00:47:21 +0000 |
|---|---|---|
| committer | Stu Grossman <grossman@cygnus> | 1995-11-15 00:47:21 +0000 |
| commit | fe2f8313f06e64b7462c921bb83c230ae1d692ac (patch) | |
| tree | 56414b24773ef786f645fb7e4f1452deb7013bbc /sim/sh | |
| parent | 97a002e72ad685304c7a5a196ae90b3146ebfa46 (diff) | |
| download | gdb-fe2f8313f06e64b7462c921bb83c230ae1d692ac.zip gdb-fe2f8313f06e64b7462c921bb83c230ae1d692ac.tar.gz gdb-fe2f8313f06e64b7462c921bb83c230ae1d692ac.tar.bz2 | |
* gencode.c: jsr, bsr and bsrf actually save pc+4 in pr, and rts
actually uses pr+0.
Diffstat (limited to 'sim/sh')
| -rw-r--r-- | sim/sh/ChangeLog | 3 | ||||
| -rw-r--r-- | sim/sh/gencode.c | 4 |
2 files changed, 4 insertions, 3 deletions
diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog index 19db378..3879582 100644 --- a/sim/sh/ChangeLog +++ b/sim/sh/ChangeLog @@ -1,6 +1,7 @@ Tue Nov 14 15:19:43 1995 Stu Grossman (grossman@cygnus.com) - * gencode.c: jsr actually saves pc+4, and rts actually uses pr+0. + * gencode.c: jsr, bsr and bsrf actually save pc+4 in pr, and rts + actually uses pr+0. Sat Oct 21 13:01:18 1995 Jim Wilson <wilson@chestnut.cygnus.com> diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c index 1c79f87..7c7f426 100644 --- a/sim/sh/gencode.c +++ b/sim/sh/gencode.c @@ -58,7 +58,7 @@ op tab[] = {"","0","and.b #<imm>,@(R0,GBR)", "11001101i8*1....", ";WBAT(GBR+R0, RBAT(GBR+R0) & i);"}, {"","","bra <bdisp12>", "1010i12.........", "ult = PC; PC=PC+(i<<1)+2;SL(ult+2);"}, - {"","","bsr <bdisp12>", "1011i12.........", "PR = PC; PC=PC+(i<<1)+2;SL(PR+2);"}, + {"","","bsr <bdisp12>", "1011i12.........", "PR = PC + 4; PC=PC+(i<<1)+2;SL(PR-2);"}, {"","","bt <bdisp8>", "10001001i8p1....", "if(T) {PC+=(SEXT(i)<<1)+2;C+=2;}"}, {"","","bf <bdisp8>", "10001011i8p1....", "if(T==0) {PC+=(SEXT(i)<<1)+2;C+=2;}"}, {"","","bt.s <bdisp8>", "10001101i8p1....","if(T) {ult = PC; PC+=(SEXT(i)<<1)+2;C+=2;SL(ult+2);}"}, @@ -200,7 +200,7 @@ op tab[] = {"","nm","dmulu.l <REG_M>,<REG_N>", "0011nnnnmmmm0101", "dmul(0,R[n],R[m]);"}, {"","nm","mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111", "abort();"}, {"","n","braf <REG_N>", "0000nnnn00100011", "ult = PC; PC+=R[n]-2;SL(ult+2);"}, - {"","n","bsrf <REG_N>", "0000nnnn00000011", "PR = PC; PC+=R[n]-2;SL(PR+2);"}, + {"","n","bsrf <REG_N>", "0000nnnn00000011", "PR = PC + 4; PC+=R[n]-2;SL(PR-2);"}, #if 0 {"divs.l <REG_M>,<REG_N>", "0100nnnnmmmm1110", "divl(0,R[n],R[m]);"}, {"divu.l <REG_M>,<REG_N>", "0100nnnnmmmm1101", "divl(0,R[n],R[m]);"}, |