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authorYao Qi <yao.qi@linaro.org>2018-02-21 11:20:03 +0000
committerYao Qi <yao.qi@linaro.org>2018-02-21 11:20:03 +0000
commitc8ec2f334c3751c28d5f952d07dea9c0558ca0a0 (patch)
tree5a6e3a58f37632ab54059d2275d77c515154c76e /sim/sh64
parentdaf6667d1f94c7e74df4076daf021cd28a2797b6 (diff)
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Class detached_regcache
jit.c uses the regcache in a slightly different way, the regcache dosen't write through to target, but it has read and write methods. If I apply regcache in record-full.c, it has the similar use pattern. This patch adds a new class detached_regcache, a register buffer, but can be read and written. Since jit.c doesn't want to write registers through to target, it uses regcache as a readonly regcache (because only readonly regcache disconnects from the target), but it adds a hole in regcache (raw_set_cached_value) in order to modify a readonly regcache. This patch fixes this hole completely. regcache inherits detached_regcache, and detached_regcache inherits readable_regcache. The ideal design is that both detached_regcache and readable_regcache inherit reg_buffer, and regcache inherit detached_regcache and regcache_read (virtual inheritance). I concern about the performance overhead of virtual inheritance, so I don't do it in the patch. gdb: 2018-02-21 Yao Qi <yao.qi@linaro.org> * jit.c (struct jit_unwind_private) <regcache>: Change its type to reg_buffer_rw *. (jit_unwind_reg_set_impl): Call raw_supply. (jit_frame_sniffer): Use reg_buffer_rw. * record-full.c (record_full_core_regbuf): Change its type. (record_full_core_open_1): Use reg_buffer_rw. (record_full_close): Likewise. (record_full_core_fetch_registers): Use regcache->raw_supply. (record_full_core_store_registers): Likewise. * regcache.c (regcache::get_register_status): Move it to reg_buffer. (regcache_raw_set_cached_value): Remove. (regcache::raw_set_cached_value): Remove. (regcache::raw_write): Call raw_supply. (regcache::raw_supply): Move it to reg_buffer_rw. * regcache.h (regcache_raw_set_cached_value): Remove. (reg_buffer_rw): New class.
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