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| author | Doug Evans <dje@google.com> | 2010-01-25 04:08:52 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 2010-01-25 04:08:52 +0000 |
| commit | d2c7a1a63b98c1add3d78ba71ffa9f2a105c1cd4 (patch) | |
| tree | 316db26ddc7d8e6777c215b4fab82f90e7369a55 /sim/sh64 | |
| parent | 3fa5b97b27c907bf60b30bc0b7d7de56561b19c7 (diff) | |
| download | gdb-d2c7a1a63b98c1add3d78ba71ffa9f2a105c1cd4.zip gdb-d2c7a1a63b98c1add3d78ba71ffa9f2a105c1cd4.tar.gz gdb-d2c7a1a63b98c1add3d78ba71ffa9f2a105c1cd4.tar.bz2 | |
common/
* cgen-accfp.c (fextsfdf): New arg how. All callers updated.
(ftruncdfsf, floatsisf, flostsidf, ufloatsisf, fixsfsi, fixdfsi,
ufixsfsi): Ditto.
* cgen-fpu.h (CGEN_FPCONV_KIND): New enum.
(struct cgen_fp_ops): Update signatures of floating point conversion
operations.
frv/
* sem.c: Regenerate.
sh64/
* cpu.h: Regenerate.
Diffstat (limited to 'sim/sh64')
| -rw-r--r-- | sim/sh64/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/sh64/cpu.h | 8 |
2 files changed, 8 insertions, 4 deletions
diff --git a/sim/sh64/ChangeLog b/sim/sh64/ChangeLog index c7dd4a0..6019b58 100644 --- a/sim/sh64/ChangeLog +++ b/sim/sh64/ChangeLog @@ -1,3 +1,7 @@ +2010-01-24 Doug Evans <dje@sebabeach.org> + + * cpu.h: Regenerate. + 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> * configure: Regenerate. diff --git a/sim/sh64/cpu.h b/sim/sh64/cpu.h index f333c06..f30d551 100644 --- a/sim/sh64/cpu.h +++ b/sim/sh64/cpu.h @@ -88,22 +88,22 @@ CPU (h_cr[(index)]) = (x);\ #define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) /* Single/Double precision floating point registers */ DF h_fsd[16]; -#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), CPU (h_fr[index])))) +#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, CPU (h_fr[index])))) #define SET_H_FSD(index, x) \ do { \ if (GET_H_PRBIT ()) {\ SET_H_DRC ((index), (x));\ } else {\ -SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\ +SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\ }\ ;} while (0) /* floating point registers for fmov */ DF h_fmov[16]; -#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index))))) +#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index))))) #define SET_H_FMOV(index, x) \ do { \ if (NOTBI (GET_H_SZBIT ())) {\ -SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\ +SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\ } else {\ if ((((((index)) & (1))) == (1))) {\ SET_H_XD ((((index)) & ((~ (1)))), (x));\ |