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| author | Joern Rennecke <joern.rennecke@embecosm.com> | 2002-06-18 15:54:44 +0000 |
|---|---|---|
| committer | Joern Rennecke <joern.rennecke@embecosm.com> | 2002-06-18 15:54:44 +0000 |
| commit | dc9feb5c97ab95cb328406040f47f20f986f0e58 (patch) | |
| tree | 958f0c1b482059b8253b4133e76d07a477b50b9e /sim/sh/interp.c | |
| parent | 7ece0d85fda7871a1fc520016c38694441f14558 (diff) | |
| download | gdb-dc9feb5c97ab95cb328406040f47f20f986f0e58.zip gdb-dc9feb5c97ab95cb328406040f47f20f986f0e58.tar.gz gdb-dc9feb5c97ab95cb328406040f47f20f986f0e58.tar.bz2 | |
* interp.c (sim_resume): Fix setting of bus error for
instruction fetch.
Diffstat (limited to 'sim/sh/interp.c')
| -rw-r--r-- | sim/sh/interp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/sh/interp.c b/sim/sh/interp.c index 286dd2d..6abff00 100644 --- a/sim/sh/interp.c +++ b/sim/sh/interp.c @@ -1717,7 +1717,7 @@ sim_resume (sd, step, siggnal) } /* Check for SIGBUS due to insn fetch. */ else if (! saved_state.asregs.exception) - saved_state.asregs.exception == SIGBUS; + saved_state.asregs.exception = SIGBUS; saved_state.asregs.ticks += get_now () - tick_start; saved_state.asregs.cycles += cycles; |