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| author | DJ Delorie <dj@redhat.com> | 2010-07-28 21:58:22 +0000 |
|---|---|---|
| committer | DJ Delorie <dj@redhat.com> | 2010-07-28 21:58:22 +0000 |
| commit | 933786524e8179ddeb0a27740d9b206352f33436 (patch) | |
| tree | 458cf4052f5038fecce2cac33c903ccb536b495f /sim/rx/cpu.h | |
| parent | d61e002c1485f3c27a2d31971480954811caa0f0 (diff) | |
| download | gdb-933786524e8179ddeb0a27740d9b206352f33436.zip gdb-933786524e8179ddeb0a27740d9b206352f33436.tar.gz gdb-933786524e8179ddeb0a27740d9b206352f33436.tar.bz2 | |
[sim/rx]
* README.txt: New.
* config.h (CYCLE_ACCURATE, CYCLE_STATS): New.
* configure.in (--enable-cycle-accurate, --enable-cycle-stats):
New. Default to enabled.
* configure: Regenerate.
* cpu.h (regs_type): Add cycle tracking info.
(reset_pipeline_stats): Declare.
(halt_pipeline_stats): Declare.
(pipeline_stats): Declare.
* main.c (done): Call pipeline_stats().
* mem.h (rx_mem_ptr): Moved to here ...
* mem.c (mem_ptr): ... from here. Rename throughout.
(mem_put_byte): Move LEDs to Port A. Add Port B to control cycle
statistics. Move UART to SCI4.
(mem_put_hi): Add TPU 1-2. TPU 1 and 2 count CPU cycles.
* reg.c (init_regs): Set Rt reg to -1 (no reg).
* rx.c: Add cycle counting and statistics throughout.
(rx_get_byte): Optimize for speed.
(decode_opcode): Likewise.
(reset_pipeline_stats): New.
(halt_pipeline_stats): New.
(pipeline_stats): New.
* trace.c (sim_disasm_one): Print cycle count.
[include/opcode]
* rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
Diffstat (limited to 'sim/rx/cpu.h')
| -rw-r--r-- | sim/rx/cpu.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/sim/rx/cpu.h b/sim/rx/cpu.h index a4afab7..74ab4b6 100644 --- a/sim/rx/cpu.h +++ b/sim/rx/cpu.h @@ -76,8 +76,24 @@ typedef struct SI r_temp; DI r_acc; + +#ifdef CYCLE_ACCURATE + /* If set, RTS/RTSD take 2 fewer cycles. */ + char fast_return; + SI link_register; + + unsigned long long cycle_count; + /* Bits saying what kind of memory operands the previous insn had. */ + int m2m; + /* Target register for load. */ + int rt; +#endif } regs_type; +#define M2M_SRC 0x01 +#define M2M_DST 0x02 +#define M2M_BOTH 0x03 + #define sp 0 #define psw 16 #define pc 17 @@ -219,6 +235,9 @@ extern unsigned int heaptop; extern unsigned int heapbottom; extern int decode_opcode (void); +extern void reset_pipeline_stats (void); +extern void halt_pipeline_stats (void); +extern void pipeline_stats (void); extern void trace_register_changes (); extern void generate_access_exception (void); |