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| author | Mike Frysinger <vapier@gentoo.org> | 2023-12-21 01:35:41 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2023-12-21 01:59:23 -0500 |
| commit | 05b9feffffb7af6986469f1be427d0c7d7fa2683 (patch) | |
| tree | 56b8e22750f9fc0f62adec6540ea41cffdf910c5 /sim/riscv | |
| parent | 92a9d946da8be990b2660c7f68b5dd0e3dbb1cc2 (diff) | |
| download | gdb-05b9feffffb7af6986469f1be427d0c7d7fa2683.zip gdb-05b9feffffb7af6986469f1be427d0c7d7fa2683.tar.gz gdb-05b9feffffb7af6986469f1be427d0c7d7fa2683.tar.bz2 | |
sim: riscv: fix -Wimplicit-fallthrough warnings
Diffstat (limited to 'sim/riscv')
| -rw-r--r-- | sim/riscv/sim-main.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index afdfcf5..4d20534 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -126,6 +126,7 @@ store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg, case CSR_INSTRETH: case CSR_TIMEH: RISCV_ASSERT_RV32 (cpu, "CSR: %s", name); + ATTRIBUTE_FALLTHROUGH; /* All the rest are immutable. */ default: |