sim: overhaul & unify endian settings management

The m4 macro has 2 args: the "wire" settings (which represents the
hardwired port behavior), and the default settings (which are used
if nothing else is specified).  If none are specified, the arch is
expected to support both, and the value will be probed based on the
user runtime options or the input program.

Only two arches today set the default value (bpf & mips).  We can
probably let this go as it only shows up in one scenario: the sim
is invoked, but with no inputs, and no user endian selection.  This
means bpf will not behave like the other arches: an error is shown
and forces the user to make a choice.  If an input program is used
though, we'll still switch the default to that.  This allows us to
remove the WITH_DEFAULT_TARGET_BYTE_ORDER setting.

For the ports that set a "wire" endian, move it to the runtime init
of the respective sim_open calls.  This allows us to change the
WITH_TARGET_BYTE_ORDER to purely a user-selected configure setting
if they want to force a specific endianness.

With all the endian logic moved to runtime selection, we can move
the configure call up to the common dir so we only process it once
across all ports.

The ppc arch was picking the wire endian based on the target used,
but since we weren't doing that for other biendian arches, we can
let this go too.  We'll rely on the input selecting the endian, or
make the user decide.

5 files changed, 11 insertions, 58 deletions

diff --git a/sim/riscv/ChangeLog b/sim/riscv/ChangeLog
index bbbd8de..5c7973f 100644
--- a/sim/riscv/ChangeLog
+++ b/sim/riscv/ChangeLog
@@ -1,3 +1,9 @@
+2021-06-17  Mike Frysinger  <vapier@gentoo.org>
+
+	* configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
+	* interp.c (sim_open): Set current_target_byte_order.
+	* aclocal.m4, configure: Regenerate.
+
 2021-06-16  Mike Frysinger  <vapier@gentoo.org>
 
 	* configure: Regenerate.
diff --git a/sim/riscv/aclocal.m4 b/sim/riscv/aclocal.m4
index 6677e0f..5aa3640 100644
--- a/sim/riscv/aclocal.m4
+++ b/sim/riscv/aclocal.m4
@@ -112,7 +112,6 @@ m4_include([../../lt~obsolete.m4])
 m4_include([../m4/sim_ac_common.m4])
 m4_include([../m4/sim_ac_option_bitsize.m4])
 m4_include([../m4/sim_ac_option_default_model.m4])
-m4_include([../m4/sim_ac_option_endian.m4])
 m4_include([../m4/sim_ac_option_hardware.m4])
 m4_include([../m4/sim_ac_option_inline.m4])
 m4_include([../m4/sim_ac_option_warnings.m4])
diff --git a/sim/riscv/configure b/sim/riscv/configure
index aa123f5..cdbedcc 100755
--- a/sim/riscv/configure
+++ b/sim/riscv/configure
@@ -634,7 +634,6 @@ LIBOBJS
 sim_reserved_bits
 sim_scache
 sim_float
-sim_alignment
 cgen_breaks
 MAINT
 MAINTAINER_MODE_FALSE
@@ -752,7 +751,6 @@ sim_inline
 sim_hw
 sim_hw_objs
 sim_hw_cflags
-sim_endian
 sim_default_model
 sim_bitsize'
 ac_subst_files=''
@@ -768,7 +766,6 @@ with_gnu_ld
 enable_libtool_lock
 enable_maintainer_mode
 enable_sim_inline
-enable_sim_endian
 enable_sim_default_model
 enable_sim_bitsize
 enable_werror
@@ -1413,8 +1410,6 @@ Optional Features:
                           sometimes confusing) to the casual installer
   --enable-sim-inline=inlines
                           Specify which functions should be inlined
-  --enable-sim-endian=endian
-                          Specify target byte endian orientation
   --enable-sim-default-model=model
                           Specify default model to simulate
   --enable-sim-bitsize=N  Specify target bitsize (32 or 64)
@@ -10747,7 +10742,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 10750 "configure"
+#line 10745 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -10853,7 +10848,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 10856 "configure"
+#line 10851 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -11148,52 +11143,6 @@ fi
 
 
 
-
-wire_endian="LITTLE"
-default_endian=""
-# Check whether --enable-sim-endian was given.
-if test "${enable_sim_endian+set}" = set; then :
-  enableval=$enable_sim_endian; case "${enableval}" in
-  b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_BIG";;
-  l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_LITTLE";;
-  yes)	 if test x"$wire_endian" != x; then
-	   sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_${wire_endian}"
-	 else
-	  if test x"$default_endian" != x; then
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_${default_endian}"
-	   else
-	     echo "No hard-wired endian for target $target" 1>&6
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_UNKNOWN"
-	   fi
-	 fi;;
-  no)	 if test x"$default_endian" != x; then
-	   sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=BFD_ENDIAN_${default_endian}"
-	 else
-	   if test x"$wire_endian" != x; then
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=BFD_ENDIAN_${wire_endian}"
-	   else
-	     echo "No default endian for target $target" 1>&6
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=BFD_ENDIAN_UNKNOWN"
-	   fi
-	 fi;;
-  *)	 as_fn_error $? "\"Unknown value $enableval for --enable-sim-endian\"" "$LINENO" 5; sim_endian="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
-  echo "Setting endian flags = $sim_endian" 6>&1
-fi
-else
-  if test x"$default_endian" != x; then
-  sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=BFD_ENDIAN_${default_endian}"
-else
-  if test x"$wire_endian" != x; then
-    sim_endian="-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_${wire_endian}"
-  else
-    sim_endian=
-  fi
-fi
-fi
-
-
 # Select the default model for the target.
 riscv_model=
 case "${target}" in
@@ -11506,8 +11455,6 @@ ac_config_commands="$ac_config_commands stamp-h"
 
 
 
-
-
 cat >confcache <<\_ACEOF
 # This file is a shell script that caches the results of configure
 # tests run on this system so they can be shared between configure
diff --git a/sim/riscv/configure.ac b/sim/riscv/configure.ac
index 421b5ba..e866c8f 100644
--- a/sim/riscv/configure.ac
+++ b/sim/riscv/configure.ac
@@ -4,8 +4,6 @@ AC_CONFIG_MACRO_DIRS([../m4 ../.. ../../config])
 
 SIM_AC_COMMON
 
-SIM_AC_OPTION_ENDIAN(LITTLE)
-
 # Select the default model for the target.
 riscv_model=
 case "${target}" in
diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index f3754da..8b96677 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -62,6 +62,9 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   SIM_DESC sd = sim_state_alloc_extra (kind, callback,
 				       sizeof (struct riscv_sim_state));
 
+  /* Set default options before parsing user options.  */
+  current_target_byte_order = BFD_ENDIAN_LITTLE;
+
   /* The cpu data is kept in a separately allocated chunk of memory.  */
   if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
     {