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| author | Mike Frysinger <vapier@gentoo.org> | 2021-06-28 21:42:56 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-06-30 01:52:51 -0400 |
| commit | 1c636da093f335cd57e7fca0fc25ae9f9e849264 (patch) | |
| tree | e33d33c678ae988d2ad31027bb2b23c8f009e34e /sim/riscv | |
| parent | f8261de1b22cc1a72ae18a2300df8b2cf7f027db (diff) | |
| download | gdb-1c636da093f335cd57e7fca0fc25ae9f9e849264.zip gdb-1c636da093f335cd57e7fca0fc25ae9f9e849264.tar.gz gdb-1c636da093f335cd57e7fca0fc25ae9f9e849264.tar.bz2 | |
sim: namespace sim_machs
We want to do a single build with all arches in one binary which means
we need to namespace sim_machs on a per-arch basis. Move it from a
global variable to the sim description structure so it can be setup at
runtime.
Changing the SIM_MODEL->num from an enum to an int is unfortunate, but
we specifically don't want to maintain a centralized list anymore, and
this was never used directly in common code, just passed to per-arch
callbacks.
Diffstat (limited to 'sim/riscv')
| -rw-r--r-- | sim/riscv/ChangeLog | 7 | ||||
| -rw-r--r-- | sim/riscv/interp.c | 3 | ||||
| -rw-r--r-- | sim/riscv/machs.c | 2 |
3 files changed, 11 insertions, 1 deletions
diff --git a/sim/riscv/ChangeLog b/sim/riscv/ChangeLog index 69c0808..1c98ed5 100644 --- a/sim/riscv/ChangeLog +++ b/sim/riscv/ChangeLog @@ -1,3 +1,10 @@ +2021-06-30 Mike Frysinger <vapier@gentoo.org> + + * interp.c (sim_open): Set STATE_MACHS. + (riscv_sim_machs): New decl. + * machs.c (sim_machs): Rename to ... + (riscv_sim_machs): ... this. + 2021-06-29 Mike Frysinger <vapier@gentoo.org> * machs.c (sim_machs): Mark const. diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c index 8b96677..8908ed1 100644 --- a/sim/riscv/interp.c +++ b/sim/riscv/interp.c @@ -53,6 +53,8 @@ free_state (SIM_DESC sd) sim_state_free (sd); } +extern const SIM_MACH * const riscv_sim_machs[]; + SIM_DESC sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd, char * const *argv) @@ -63,6 +65,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, sizeof (struct riscv_sim_state)); /* Set default options before parsing user options. */ + STATE_MACHS (sd) = riscv_sim_machs; current_target_byte_order = BFD_ENDIAN_LITTLE; /* The cpu data is kept in a separately allocated chunk of memory. */ diff --git a/sim/riscv/machs.c b/sim/riscv/machs.c index eb75a1d..339e5ba 100644 --- a/sim/riscv/machs.c +++ b/sim/riscv/machs.c @@ -111,7 +111,7 @@ static const SIM_MACH rv128i_mach = #endif /* Order matters here. */ -const SIM_MACH * const sim_machs[] = +const SIM_MACH * const riscv_sim_machs[] = { #if WITH_TARGET_WORD_BITSIZE >= 128 &rv128i_mach, |