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| author | Mike Frysinger <vapier@gentoo.org> | 2022-12-22 23:10:38 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2022-12-23 08:32:58 -0500 |
| commit | f3e1a3e6fa80c20b7ab5e968330ae69fe0a3cd81 (patch) | |
| tree | bbc68dacd2636833055dff2bb4057171c212fd02 /sim/riscv/interp.c | |
| parent | f625c714c2c5a9b6fdc5f4424730e6140c8d0bb9 (diff) | |
| download | gdb-f3e1a3e6fa80c20b7ab5e968330ae69fe0a3cd81.zip gdb-f3e1a3e6fa80c20b7ab5e968330ae69fe0a3cd81.tar.gz gdb-f3e1a3e6fa80c20b7ab5e968330ae69fe0a3cd81.tar.bz2 | |
sim: riscv: move arch-specific settings to internal header
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
We can also move the machs.h include out since the model logic was all
generalized from compile-time to runtime last year.
Diffstat (limited to 'sim/riscv/interp.c')
| -rw-r--r-- | sim/riscv/interp.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c index 6bd0bf2..a49ad04 100644 --- a/sim/riscv/interp.c +++ b/sim/riscv/interp.c @@ -27,6 +27,8 @@ #include "sim-main.h" #include "sim-options.h" #include "target-newlib-syscall.h" + +#include "riscv-sim.h" void sim_engine_run (SIM_DESC sd, |