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authorDimitar Dimitrov <dimitar@dinux.eu>2020-11-12 22:23:26 +0200
committerDimitar Dimitrov <dimitar@dinux.eu>2020-11-12 22:41:10 +0200
commite57cf1f2cdf819946494becf282e47194aa6216d (patch)
treeb30063156b4d1d911a625aaf4b53c8155ab25dbf /sim/pru
parent1350c3b47a6fed106d1f6814376dd12dea8a14d0 (diff)
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sim: pru: Add support for LMBD instruction
Binutils support for LMBD instruction was merged [1]. So add it also to simulator. LMBD instruction does left-most-bit-detection. It returns 32 if the given bit value is not found in the provided word value. [1] https://sourceware.org/pipermail/binutils/2020-October/113901.html sim/pru/ChangeLog: * pru.h (RS1SEL): New macro. (RS1_WIDTH): New macro. * pru.isa: Describe the LMBD instruction. sim/testsuite/sim/pru/ChangeLog: * lmbd.s: New test.
Diffstat (limited to 'sim/pru')
-rw-r--r--sim/pru/ChangeLog6
-rw-r--r--sim/pru/pru.h2
-rw-r--r--sim/pru/pru.isa15
3 files changed, 23 insertions, 0 deletions
diff --git a/sim/pru/ChangeLog b/sim/pru/ChangeLog
index bccc3ef..ad9aff9 100644
--- a/sim/pru/ChangeLog
+++ b/sim/pru/ChangeLog
@@ -1,3 +1,9 @@
+2020-11-12 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * pru.h (RS1SEL): New macro.
+ (RS1_WIDTH): New macro.
+ * pru.isa: Describe the LMBD instruction.
+
2019-09-23 Dimitar Dimitrov <dimitar@dinux.eu>
* Makefile.in: New file.
diff --git a/sim/pru/pru.h b/sim/pru/pru.h
index 240fc30..cbcc3ef 100644
--- a/sim/pru/pru.h
+++ b/sim/pru/pru.h
@@ -58,6 +58,8 @@
#define XBBO_BASEREG (CPU.regs[GET_INSN_FIELD (RS1, inst)])
+#define RS1SEL GET_INSN_FIELD (RS1SEL, inst)
+#define RS1_WIDTH regsel_width (RS1SEL)
#define RDSEL GET_INSN_FIELD (RDSEL, inst)
#define RD_WIDTH regsel_width (RDSEL)
#define RD_REGN GET_INSN_FIELD (RD, inst)
diff --git a/sim/pru/pru.isa b/sim/pru/pru.isa
index 0501545..c7860d0 100644
--- a/sim/pru/pru.isa
+++ b/sim/pru/pru.isa
@@ -247,3 +247,18 @@ INSTRUCTION (iloop,
LOOP_IN_PROGRESS = 1;
PC++;
})
+
+INSTRUCTION (lmbd,
+ {
+ int lmbd_i;
+
+ OP2 = (IO ? IMM8 : RS2);
+
+ for (lmbd_i = RS1_WIDTH - 1; lmbd_i >= 0; lmbd_i--)
+ {
+ if (!(((RS1 >> lmbd_i) ^ OP2) & 1))
+ break;
+ }
+ RD = (lmbd_i < 0) ? 32 : lmbd_i;
+ PC++;
+ })