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| author | Andrew Cagney <cagney@redhat.com> | 2002-03-23 21:18:31 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2002-03-23 21:18:31 +0000 |
| commit | ec80ed8088b19b7b4de388667d59f6ddeadef1ad (patch) | |
| tree | 2864cd2561824ba7c86da6d61ba7bd8cbb938695 /sim/ppc | |
| parent | 3b45974e920a793a42fb1f575d9a53617c554d66 (diff) | |
| download | gdb-ec80ed8088b19b7b4de388667d59f6ddeadef1ad.zip gdb-ec80ed8088b19b7b4de388667d59f6ddeadef1ad.tar.gz gdb-ec80ed8088b19b7b4de388667d59f6ddeadef1ad.tar.bz2 | |
From 2001-12-09 Julien Ducourthial <jducourt@noos.fr>:
* ppc-instructions (lswx): Do the register control with the
register count. Initialize the right register in the loop.
(mtfsfi) : Correct prefix for the instruction.
Diffstat (limited to 'sim/ppc')
| -rw-r--r-- | sim/ppc/ChangeLog | 7 | ||||
| -rw-r--r-- | sim/ppc/ppc-instructions | 14 |
2 files changed, 14 insertions, 7 deletions
diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog index 25d96ea..b3a5651 100644 --- a/sim/ppc/ChangeLog +++ b/sim/ppc/ChangeLog @@ -1,3 +1,10 @@ +2002-03-23 Andrew Cagney <ac131313@redhat.com> + + From 2001-12-09 Julien Ducourthial <jducourt@noos.fr>: + * ppc-instructions (lswx): Do the register control with the + register count. Initialize the right register in the loop. + (mtfsfi) : Correct prefix for the instruction. + 2002-02-24 Andrew Cagney <ac131313@redhat.com> From wiz at danbala: diff --git a/sim/ppc/ppc-instructions b/sim/ppc/ppc-instructions index 25a9d78..6ba0090 100644 --- a/sim/ppc/ppc-instructions +++ b/sim/ppc/ppc-instructions @@ -2275,11 +2275,11 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, r = RT - 1; i = 32; nr = (n + 3) / 4; - if (((RT + n >= 32) - ? ((RA >= RT || RA < (RT + n) % 32) - || (RB >= RT || RB < (RT + n) % 32)) - : ((RA >= RT && RA < RT + n) - || (RB >= RT && RB < RT + n))) + if (((RT + nr >= 32) + ? ((RA >= RT || RA < (RT + nr) % 32) + || (RB >= RT || RB < (RT + nr) % 32)) + : ((RA >= RT && RA < RT + nr) + || (RB >= RT && RB < RT + nr))) || (RT == RA || RT == RB)) program_interrupt(processor, cia, illegal_instruction_program_interrupt); @@ -2288,7 +2288,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, while (n > 0) { if (i == 32) { r = (r + 1) % 32; - GPR(i) = 0; + GPR(r) = 0; } GPR(r) |= INSERTED(MEM(unsigned, EA, 1), i, i+7); i = i + 8; @@ -4582,7 +4582,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, FPSCR_SET(BFA, 0); /* FPSCR_END fixes up FEX/VX */ FPSCR_END(0); -0.64,6.BF,9./,11./,16.U,20./,21.134,31.Rc:X:f::Move To FPSCR Field Immediate +0.63,6.BF,9./,11./,16.U,20./,21.134,31.Rc:X:f::Move To FPSCR Field Immediate FPSCR_BEGIN; FPSCR_SET(BF, U); FPSCR_END(Rc); |