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| author | Michael Meissner <gnu@the-meissners.org> | 1995-11-03 19:37:28 +0000 |
|---|---|---|
| committer | Michael Meissner <gnu@the-meissners.org> | 1995-11-03 19:37:28 +0000 |
| commit | 056e975cfe9122850c7e7427269912fbbe9a7626 (patch) | |
| tree | 3c8e416826f83cd5c450649343f4ad4f19e54b70 /sim/ppc | |
| parent | 0140d7463da2dc600370748410c2ff138b9132e2 (diff) | |
| download | gdb-056e975cfe9122850c7e7427269912fbbe9a7626.zip gdb-056e975cfe9122850c7e7427269912fbbe9a7626.tar.gz gdb-056e975cfe9122850c7e7427269912fbbe9a7626.tar.bz2 | |
Add 2 config flags that were missing; make data cache instructions be nops
Diffstat (limited to 'sim/ppc')
| -rw-r--r-- | sim/ppc/ChangeLog | 8 | ||||
| -rw-r--r-- | sim/ppc/Makefile.in | 2 | ||||
| -rw-r--r-- | sim/ppc/ppc-instructions | 9 |
3 files changed, 19 insertions, 0 deletions
diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog index 58cb18f..6701151 100644 --- a/sim/ppc/ChangeLog +++ b/sim/ppc/ChangeLog @@ -1,3 +1,11 @@ +Fri Nov 3 11:37:24 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc-instructions (data cache instructions): Make all data cache + instructions nops instead of invalid instructions. + + * Makefile.in (CONFIG_CFLAGS): Add ALIGNMENT_CFLAGS and + TIMEBASE_CFLAGS which weren't included. + Thu Nov 2 08:54:04 1995 Michael Meissner <meissner@tiktok.cygnus.com> * Makefile.in: Uncomment built file dependencies. diff --git a/sim/ppc/Makefile.in b/sim/ppc/Makefile.in index e720458..b56e6e5 100644 --- a/sim/ppc/Makefile.in +++ b/sim/ppc/Makefile.in @@ -88,6 +88,8 @@ CONFIG_CFLAGS = $(BSWAP_CFLAGS) \ $(BITSIZE_CFLAGS) \ $(HOSTBITSIZE_CFLAGS) \ $(ENV_CFLAGS) \ + $(TIMEBASE_CFLAGS) \ + $(ALIGNMENT_CFLAGS) \ $(FLOAT_CFLAGS) \ $(TRACE_CFLAGS) \ $(ASSERT_CFLAGS) \ diff --git a/sim/ppc/ppc-instructions b/sim/ppc/ppc-instructions index 2fa9c6b..8d2ca05 100644 --- a/sim/ppc/ppc-instructions +++ b/sim/ppc/ppc-instructions @@ -2297,10 +2297,19 @@ void::function::invalid_arithemetic_operation:cpu *processor, unsigned_word cia, # 0.31,6./,11.RA,16.RB,21.278,31./:X:::Data Cache Block Touch + ; /* nop for now */ + 0.31,6./,11.RA,16.RB,21.246,31./:X:::Data Cache Block Touch for Store + ; /* nop for now */ + 0.31,6./,11.RA,16.RB,21.1014,31./:X:::Data Cache Block set to Zero + ; /* nop for now */ + 0.31,6./,11.RA,16.RB,21.54,31./:X:::Data Cache Block Store + ; /* nop for now */ + 0.31,6./,11.RA,16.RB,21.86,31./:X:::Data Cache Block Flush + ; /* nop for now */ # # II.3.3 Envorce In-order Execution of I/O Instruction |