New changes from Andrew

1 files changed, 92 insertions, 0 deletions

diff --git a/sim/ppc/ppc-opcode-simple b/sim/ppc/ppc-opcode-simple
new file mode 100644
index 0000000..b3a1316
--- /dev/null
+++ b/sim/ppc/ppc-opcode-simple
@@ -0,0 +1,92 @@
+#
+#   This file is part of the program psim.
+#
+#   Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
+#
+#   This program is free software; you can redistribute it and/or modify
+#   it under the terms of the GNU General Public License as published by
+#   the Free Software Foundation; either version 2 of the License, or
+#   (at your option) any later version.
+#
+#   This program is distributed in the hope that it will be useful,
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#   GNU General Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License
+#   along with this program; if not, write to the Free Software
+#   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+#   Instruction decode:
+#
+#   The table that follows is used by gen to construct a decision tree
+#   that can identify each possible instruction.  Gen then outputs this
+#   decision tree as (according to config) a table or switch statement
+#   as the function idecode.
+#
+#   In parallel to this, as mentioned above, WITH_EXPANDED_SEMANTICS
+#   determines of the semantic functions themselves should be expanded
+#   in a similar way.
+#
+#   The table contains the following entries:
+#
+#   <valid>
+#
+#   Must be 1 for the entry to be considered.  The last entry must be
+#   zero.
+#	
+#   <first>
+#   <last>
+#
+#   Range of bits (within the instruction) that should be searched for
+#   an instruction field.  Within such ranges, gen looks for opcodes
+#   (constants), registers (strings) and reserved bits (slash) and
+#   according to the rules that follows includes or excludes them from
+#   a possible instruction field.
+#
+#   <force_first>
+#   <force_last>
+#
+#   If an instructioin field was found, enlarge the field size so that
+#   it is forced to at least include bits starting from <force_first>
+#   (<force_last>).  To stop this occuring, use <force_first> = <last>
+#   + 1 and <force_last> = <first> - 1.
+#
+#   <force_slash>
+#
+#   Treat `/' fields as a constant instead of variable when looking for
+#   an instruction field.
+#
+#   <force_expansion>
+#
+#   Treat any contained register (string) fields as constant when
+#   determining the instruction field.  For the instruction decode (and
+#   controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
+#   what would otherwize be non constant bits of an instruction.
+#
+#   <use_switch>
+#
+#   Should this table be expanded using a switch statement (val 1) and
+#   if so, should it be padded with entries so as to force the compiler
+#   to generate a jump table (val 2).
+#
+#   <special_mask>
+#   <special_value>
+#   <special_rule>
+#
+#   Special rule to fine tune how specific (or groups) of instructions
+#   are expanded.  The applicability of the rule is determined by
+#
+#     <special_mask> != 0 && (instruction> & <special_mask>) == <special_value>
+#
+#   Where <instruction> is obtained by looking only at constant fields
+#   with in an instructions spec.  When determining an expansion, the
+#   rule is only considered when a node contains a single instruction.
+#   <special_rule> can be any of:
+#
+#        0: for this instruction, expand by earlier rules
+#   	1: expand bits <force_low> .. <force_hi> only
+#	2: boolean expansion of only zero/non-zero cases
+#
+ 0: 5: 0: 5:0::              1:0x00000000:0x00000000:0
+21:31:32:-1:0::              1:0x00000000:0x00000000:0