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| author | Anthony Green <green@moxielogic.com> | 2014-12-24 08:37:16 -0500 |
|---|---|---|
| committer | Anthony Green <green@moxielogic.com> | 2014-12-24 08:38:09 -0500 |
| commit | ed4fd7b7f30020dfdcd79cfd1e36672395f905d7 (patch) | |
| tree | 6af047d7b04c65fc95b4bed0c2d0aed9040aa2c5 /sim/moxie/interp.c | |
| parent | 0be40ae409724495a434de404bda39c53bb167a0 (diff) | |
| download | gdb-ed4fd7b7f30020dfdcd79cfd1e36672395f905d7.zip gdb-ed4fd7b7f30020dfdcd79cfd1e36672395f905d7.tar.gz gdb-ed4fd7b7f30020dfdcd79cfd1e36672395f905d7.tar.bz2 | |
Add support for moxie's mul.x and umul.x instructions
Diffstat (limited to 'sim/moxie/interp.c')
| -rw-r--r-- | sim/moxie/interp.c | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c index fdb6528..fdd94af 100644 --- a/sim/moxie/interp.c +++ b/sim/moxie/interp.c @@ -622,8 +622,30 @@ sim_resume (sd, step, siggnal) cpu.asregs.regs[a] = (int) bv & 0xffff; } break; - case 0x14: /* bad */ - case 0x15: /* bad */ + case 0x14: /* mul.x */ + { + int a = (inst >> 4) & 0xf; + int b = inst & 0xf; + unsigned av = cpu.asregs.regs[a]; + unsigned bv = cpu.asregs.regs[b]; + TRACE("mul.x"); + signed long long r = + (signed long long) av * (signed long long) bv; + cpu.asregs.regs[a] = r >> 32; + } + break; + case 0x15: /* umul.x */ + { + int a = (inst >> 4) & 0xf; + int b = inst & 0xf; + unsigned av = cpu.asregs.regs[a]; + unsigned bv = cpu.asregs.regs[b]; + TRACE("umul.x"); + unsigned long long r = + (unsigned long long) av * (unsigned long long) bv; + cpu.asregs.regs[a] = r >> 32; + } + break; case 0x16: /* bad */ case 0x17: /* bad */ case 0x18: /* bad */ |