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| author | Anthony Green <green@redhat.com> | 2009-05-10 13:25:57 +0000 |
|---|---|---|
| committer | Anthony Green <green@redhat.com> | 2009-05-10 13:25:57 +0000 |
| commit | 77176dfc67dc5b8d8984af31ae195b95bac8f8e5 (patch) | |
| tree | e94387620020420b1bf66c01a0ca2323bc10dd97 /sim/moxie/interp.c | |
| parent | bd518e6be47d7fb7a38acbeb401356f9eb858210 (diff) | |
| download | gdb-77176dfc67dc5b8d8984af31ae195b95bac8f8e5.zip gdb-77176dfc67dc5b8d8984af31ae195b95bac8f8e5.tar.gz gdb-77176dfc67dc5b8d8984af31ae195b95bac8f8e5.tar.bz2 | |
Add missing break statemenets.
Diffstat (limited to 'sim/moxie/interp.c')
| -rw-r--r-- | sim/moxie/interp.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c index 2be561c..dd87648 100644 --- a/sim/moxie/interp.c +++ b/sim/moxie/interp.c @@ -460,6 +460,7 @@ sim_resume (sd, step, siggnal) TRACE("gsr"); cpu.asregs.regs[a] = cpu.asregs.sregs[v]; } + break; case 0x03: /* ssr */ { int a = (inst >> 8) & 0xf; @@ -467,6 +468,7 @@ sim_resume (sd, step, siggnal) TRACE("ssr"); cpu.asregs.sregs[v] = cpu.asregs.regs[a]; } + break; default: TRACE("SIGILL2"); cpu.asregs.exception = SIGILL; |