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| author | Anthony Green <green@moxielogic.com> | 2014-12-12 08:44:19 -0500 |
|---|---|---|
| committer | Anthony Green <green@moxielogic.com> | 2014-12-12 08:45:25 -0500 |
| commit | c784b1150407a85946f9d45553893349de45a577 (patch) | |
| tree | d9104d120cb4285da8ebee4103bf6eb92c3b051a /sim/moxie/interp.c | |
| parent | 26047f76c056cfe04e917a249beed66d046b7eb6 (diff) | |
| download | gdb-c784b1150407a85946f9d45553893349de45a577.zip gdb-c784b1150407a85946f9d45553893349de45a577.tar.gz gdb-c784b1150407a85946f9d45553893349de45a577.tar.bz2 | |
Add zex instruction support for moxie port
Diffstat (limited to 'sim/moxie/interp.c')
| -rw-r--r-- | sim/moxie/interp.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c index 4362c66..fdb6528 100644 --- a/sim/moxie/interp.c +++ b/sim/moxie/interp.c @@ -604,8 +604,24 @@ sim_resume (sd, step, siggnal) cpu.asregs.regs[a] = (int) bv; } break; - case 0x12: /* bad */ - case 0x13: /* bad */ + case 0x12: /* zex.b */ + { + int a = (inst >> 4) & 0xf; + int b = inst & 0xf; + signed char bv = cpu.asregs.regs[b]; + TRACE("zex.b"); + cpu.asregs.regs[a] = (int) bv & 0xff; + } + break; + case 0x13: /* zex.s */ + { + int a = (inst >> 4) & 0xf; + int b = inst & 0xf; + signed short bv = cpu.asregs.regs[b]; + TRACE("zex.s"); + cpu.asregs.regs[a] = (int) bv & 0xffff; + } + break; case 0x14: /* bad */ case 0x15: /* bad */ case 0x16: /* bad */ |