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| author | Jeff Law <law@redhat.com> | 1996-12-10 22:10:07 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1996-12-10 22:10:07 +0000 |
| commit | 95d18eb74d629b32e817a629fbbf8421d3fbd690 (patch) | |
| tree | 6d94548c86d30b5f6fd1a667cc3e936151f74184 /sim/mn10300/simops.c | |
| parent | 60b43c4bdedfea6b6b394506956a5f7847a96494 (diff) | |
| download | gdb-95d18eb74d629b32e817a629fbbf8421d3fbd690.zip gdb-95d18eb74d629b32e817a629fbbf8421d3fbd690.tar.gz gdb-95d18eb74d629b32e817a629fbbf8421d3fbd690.tar.bz2 | |
* simops.c (REG0_4): Define.
Use REG0_4 for indexed loads/stores.
Fixes bugs exposed after minor codegen improvements in the compiler.
Diffstat (limited to 'sim/mn10300/simops.c')
| -rw-r--r-- | sim/mn10300/simops.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c index 24bdfca..02bf7b2 100644 --- a/sim/mn10300/simops.c +++ b/sim/mn10300/simops.c @@ -15,6 +15,7 @@ #define REG0(X) ((X) & 0x3) #define REG1(X) (((X) & 0xc) >> 2) +#define REG0_4(X) (((X) & 0x30) >> 4) #define REG0_8(X) (((X) & 0x300) >> 8) #define REG1_8(X) (((X) & 0xc00) >> 10) #define REG0_16(X) (((X) & 0x30000) >> 16) @@ -167,7 +168,7 @@ void OP_FCB40000 (insn, extension) void OP_F300 (insn, extension) unsigned long insn, extension; { - State.regs[REG_D0 + REG0_8 (insn)] + State.regs[REG_D0 + REG0_4 (insn)] = load_mem ((State.regs[REG_A0 + REG0 (insn)] + State.regs[REG_D0 + REG1 (insn)]), 4); } @@ -250,7 +251,7 @@ void OP_FCB00000 (insn, extension) void OP_F380 (insn, extension) unsigned long insn, extension; { - State.regs[REG_A0 + REG0_8 (insn)] + State.regs[REG_A0 + REG0_4 (insn)] = load_mem ((State.regs[REG_A0 + REG0 (insn)] + State.regs[REG_D0 + REG1 (insn)]), 4); } @@ -344,7 +345,7 @@ void OP_F340 (insn, extension) { store_mem ((State.regs[REG_A0 + REG0 (insn)] + State.regs[REG_D0 + REG1 (insn)]), 4, - State.regs[REG_D0 + REG0_8 (insn)]); + State.regs[REG_D0 + REG0_4 (insn)]); } /* mov dm, (abs16) */ @@ -426,7 +427,7 @@ void OP_F3C0 (insn, extension) { store_mem ((State.regs[REG_A0 + REG0 (insn)] + State.regs[REG_D0 + REG1 (insn)]), 4, - State.regs[REG_A0 + REG0_8 (insn)]); + State.regs[REG_A0 + REG0_4 (insn)]); } /* mov am, (abs16) */ @@ -554,7 +555,7 @@ void OP_FCB80000 (insn, extension) void OP_F400 (insn, extension) unsigned long insn, extension; { - State.regs[REG_D0 + REG0_8 (insn)] + State.regs[REG_D0 + REG0_4 (insn)] = load_mem ((State.regs[REG_A0 + REG0 (insn)] + State.regs[REG_D0 + REG1 (insn)]), 1); } @@ -639,7 +640,7 @@ void OP_F440 (insn, extension) { store_mem ((State.regs[REG_A0 + REG0 (insn)] + State.regs[REG_D0 + REG1 (insn)]), 1, - State.regs[REG_D0 + REG0_8 (insn)]); + State.regs[REG_D0 + REG0_4 (insn)]); } /* movbu dm, (abs16) */ @@ -719,7 +720,7 @@ void OP_FCBC0000 (insn, extension) void OP_F480 (insn, extension) unsigned long insn, extension; { - State.regs[REG_D0 + REG0_8 (insn)] + State.regs[REG_D0 + REG0_4 (insn)] = load_mem ((State.regs[REG_A0 + REG0 (insn)] + State.regs[REG_D0 + REG1 (insn)]), 2); } @@ -804,7 +805,7 @@ void OP_F4C0 (insn, extension) { store_mem ((State.regs[REG_A0 + REG0 (insn)] + State.regs[REG_D0 + REG1 (insn)]), 2, - State.regs[REG_D0 + REG0_8 (insn)]); + State.regs[REG_D0 + REG0_4 (insn)]); } /* movhu dm, (abs16) */ |