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authorJeff Law <law@redhat.com>1996-11-26 22:58:24 +0000
committerJeff Law <law@redhat.com>1996-11-26 22:58:24 +0000
commit73e6529893a8146ff7aaaa9b7c2fca8c8817da1e (patch)
tree48c95bb4538ba1698de841f694f04808dbea6cb0 /sim/mn10300/mn10300_sim.h
parentd45358c6a7f618f3b4bf967ba7853e17ceab73f6 (diff)
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* mn10300_sim.h (PSW_*): Define for CC status tracking.
(REG_D0, REG_A0, REG_SP): Define. * simops.c: Implement "add", "addc" and a few other random instructions. Starting to simulate instructions for the mn10300. Executes some of the crt0 code now!
Diffstat (limited to 'sim/mn10300/mn10300_sim.h')
-rw-r--r--sim/mn10300/mn10300_sim.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h
index 4170c26..245e8bd 100644
--- a/sim/mn10300/mn10300_sim.h
+++ b/sim/mn10300/mn10300_sim.h
@@ -68,10 +68,19 @@ struct _state
extern uint32 OP[4];
extern struct simops Simops[];
+extern unsigned long insn, extension;
#define PC (State.pc)
#define PSW (State.sregs[0])
+#define PSW_V 0x1
+#define PSW_C 0x2
+#define PSW_N 0x4
+#define PSW_Z 0x8
+
+#define REG_D0 0
+#define REG_A0 4
+#define REG_SP 8
#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)