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author | Jeff Law <law@redhat.com> | 1997-05-20 23:53:47 +0000 |
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committer | Jeff Law <law@redhat.com> | 1997-05-20 23:53:47 +0000 |
commit | 003c91bec4849e4a5b54d6e81383a4ff4376e996 (patch) | |
tree | 79bd3bbdf1600531f18465bb1d9cdb826b559211 /sim/mn10300/interp.c | |
parent | 4e39c0f9b2c6500cd9d0fc63ad4daea7be63d0fc (diff) | |
download | gdb-003c91bec4849e4a5b54d6e81383a4ff4376e996.zip gdb-003c91bec4849e4a5b54d6e81383a4ff4376e996.tar.gz gdb-003c91bec4849e4a5b54d6e81383a4ff4376e996.tar.bz2 |
* interp.c: Replace all references to load_mem and store_mem
with references to load_byte, load_half, load_3_byte, load_word
and store_byte, store_half, store_3_byte, store_word.
(INLINE): Delete definition.
(load_mem_big): Likewise.
(max_mem): Make it global.
(dispatch): Make this function inline.
(load_mem, store_mem): Delete functions.
* mn10300_sim.h (INLINE): Define.
(RLW): Delete unused definition.
(load_mem, store_mem): Delete declarations.
(load_mem_big): New definition.
(load_byte, load_half, load_3_byte, load_word): New functions.
(store_byte, store_half, store_3_byte, store_word): New functions.
* simops.c: Replace all references to load_mem and store_mem
with references to load_byte, load_half, load_3_byte, load_word
and store_byte, store_half, store_3_byte, store_word.
Diffstat (limited to 'sim/mn10300/interp.c')
-rw-r--r-- | sim/mn10300/interp.c | 108 |
1 files changed, 23 insertions, 85 deletions
diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c index affa4ab..7f29f76 100644 --- a/sim/mn10300/interp.c +++ b/sim/mn10300/interp.c @@ -4,14 +4,6 @@ #include "mn10300_sim.h" -#ifndef INLINE -#ifdef __GNUC__ -#define INLINE inline -#else -#define INLINE -#endif -#endif - host_callback *mn10300_callback; int mn10300_debug; static SIM_OPEN_KIND sim_kind; @@ -234,62 +226,6 @@ put_word (addr, data) a[3] = (data >> 24) & 0xff; } -uint32 -load_mem (addr, len) - SIM_ADDR addr; - int len; -{ - uint8 *p = addr + State.mem; - - if (addr > max_mem) - abort (); - - switch (len) - { - case 1: - return p[0]; - case 2: - return p[1] << 8 | p[0]; - case 3: - return p[2] << 16 | p[1] << 8 | p[0]; - case 4: - return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0]; - default: - abort (); - } -} - -void -store_mem (addr, len, data) - SIM_ADDR addr; - int len; - uint32 data; -{ - uint8 *p = addr + State.mem; - - if (addr > max_mem) - abort (); - - switch (len) - { - case 1: - p[0] = data; - return; - case 2: - p[0] = data; - p[1] = data >> 8; - return; - case 4: - p[0] = data; - p[1] = data >> 8; - p[2] = data >> 16; - p[3] = data >> 24; - return; - default: - abort (); - } -} - void sim_size (power) int power; @@ -326,7 +262,7 @@ sim_write (sd, addr, buffer, size) init_system (); for (i = 0; i < size; i++) - store_mem (addr + i, 1, buffer[i]); + store_byte (addr + i, buffer[i]); return size; } @@ -348,8 +284,9 @@ compare_simops (arg1, arg2) } SIM_DESC -sim_open (kind,argv) +sim_open (kind,cb,argv) SIM_OPEN_KIND kind; + host_callback *cb; char **argv; { struct simops *s; @@ -357,6 +294,8 @@ sim_open (kind,argv) char **p; int i; + mn10300_callback = cb; + /* Sort the opcode array from smallest opcode to largest. This will generally improve simulator performance as the smaller opcodes are generally preferred to the larger opcodes. */ @@ -749,9 +688,9 @@ sim_resume (sd, step, siggnal) case 0x3a: case 0x3b: case 0xcc: - insn = load_mem (PC, 1); + insn = load_byte (PC); insn <<= 16; - insn |= load_mem (PC + 1, 2); + insn |= load_half (PC + 1); extension = 0; dispatch (insn, extension, 3); break; @@ -777,7 +716,7 @@ sim_resume (sd, step, siggnal) { insn = inst; insn <<= 16; - insn |= load_mem (PC + 2, 2); + insn |= load_half (PC + 2); extension = 0; } dispatch (insn, extension, 4); @@ -785,18 +724,18 @@ sim_resume (sd, step, siggnal) /* Five byte insns. */ case 0xcd: - insn = load_mem (PC, 1); + insn = load_byte (PC); insn <<= 24; - insn |= (load_mem (PC + 1, 2) << 8); - insn |= load_mem (PC + 3, 1); - extension = load_mem (PC + 4, 1); + insn |= (load_half (PC + 1) << 8); + insn |= load_byte (PC + 3); + extension = load_byte (PC + 4); dispatch (insn, extension, 5); break; case 0xdc: - insn = load_mem (PC, 1); + insn = load_byte (PC); insn <<= 24; - extension = load_mem (PC + 1, 4); + extension = load_word (PC + 1); insn |= (extension & 0xffffff00) >> 8; extension &= 0xff; dispatch (insn, extension, 5); @@ -806,29 +745,29 @@ sim_resume (sd, step, siggnal) case 0xfc: case 0xfd: insn = (inst << 16); - extension = load_mem (PC + 2, 4); + extension = load_word (PC + 2); insn |= ((extension & 0xffff0000) >> 16); extension &= 0xffff; dispatch (insn, extension, 6); break; case 0xdd: - insn = load_mem (PC, 1) << 24; - extension = load_mem (PC + 1, 4); + insn = load_byte (PC) << 24; + extension = load_word (PC + 1); insn |= ((extension >> 8) & 0xffffff); extension = (extension & 0xff) << 16; - extension |= load_mem (PC + 5, 1) << 8; - extension |= load_mem (PC + 6, 1); + extension |= load_byte (PC + 5) << 8; + extension |= load_byte (PC + 6); dispatch (insn, extension, 7); break; case 0xfe: insn = inst << 16; - extension = load_mem (PC + 2, 4); + extension = load_word (PC + 2); insn |= ((extension >> 16) & 0xffff); extension <<= 8; extension &= 0xffff00; - extension |= load_mem (PC + 6, 1); + extension |= load_byte (PC + 6); dispatch (insn, extension, 7); break; @@ -898,8 +837,7 @@ sim_kill (sd) } void -sim_set_callbacks (sd, p) - SIM_DESC sd; +sim_set_callbacks (p) host_callback *p; { mn10300_callback = p; @@ -949,7 +887,7 @@ sim_read (sd, addr, buffer, size) { int i; for (i = 0; i < size; i++) - buffer[i] = load_mem (addr + i, 1); + buffer[i] = load_byte (addr + i); return size; } |