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| author | Joyce Janczyn <janczyn@cygnus> | 1998-08-26 13:31:38 +0000 |
|---|---|---|
| committer | Joyce Janczyn <janczyn@cygnus> | 1998-08-26 13:31:38 +0000 |
| commit | ef4d20e91566e7f6ee7133ccee235f6922bd6df5 (patch) | |
| tree | 37ba058df116aad44ea867bbf02f3f47b34a6dda /sim/mn10300/ChangeLog | |
| parent | 7c71c3ea984e667edb041395fc780ac40088b002 (diff) | |
| download | gdb-ef4d20e91566e7f6ee7133ccee235f6922bd6df5.zip gdb-ef4d20e91566e7f6ee7133ccee235f6922bd6df5.tar.gz gdb-ef4d20e91566e7f6ee7133ccee235f6922bd6df5.tar.bz2 | |
Regress yesterday's change to jmp instruction -- it has deceiving syntax.
Also tidy up some code to match documentation and fix div, divu by 0.
Diffstat (limited to 'sim/mn10300/ChangeLog')
| -rw-r--r-- | sim/mn10300/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index 251f478..1278b76 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,8 @@ +Wed Aug 26 09:29:38 1998 Joyce Janczyn <janczyn@cygnus.com> + + * mn10300.igen (div,divu): Fix divide instructions so divide by 0 + behaves like the hardware. + Tue Aug 25 16:46:59 1998 Joyce Janczyn <janczyn@cygnus.com> * mn10300.igen (OP_F0F4): Need to load contents of register AN0 |