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author | Andrew Cagney <cagney@redhat.com> | 2004-11-12 16:45:32 +0000 |
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committer | Andrew Cagney <cagney@redhat.com> | 2004-11-12 16:45:32 +0000 |
commit | c46ec85da270994b50ccc5c8de0f1751cf3a0683 (patch) | |
tree | a5941765ceb8c03216c7a82f0a9f92c02b368a39 /sim/mn10200 | |
parent | 4fab48b9c48377889af365990e148954c3343287 (diff) | |
download | gdb-c46ec85da270994b50ccc5c8de0f1751cf3a0683.zip gdb-c46ec85da270994b50ccc5c8de0f1751cf3a0683.tar.gz gdb-c46ec85da270994b50ccc5c8de0f1751cf3a0683.tar.bz2 |
2004-11-12 Andrew Cagney <cagney@gnu.org>
* d30v, fr30, mn10200, z8k: Delete directory.
Diffstat (limited to 'sim/mn10200')
-rw-r--r-- | sim/mn10200/ChangeLog | 472 | ||||
-rw-r--r-- | sim/mn10200/Makefile.in | 52 | ||||
-rw-r--r-- | sim/mn10200/acconfig.h | 15 | ||||
-rw-r--r-- | sim/mn10200/config.in | 158 | ||||
-rwxr-xr-x | sim/mn10200/configure | 4024 | ||||
-rw-r--r-- | sim/mn10200/configure.in | 10 | ||||
-rw-r--r-- | sim/mn10200/gencode.c | 154 | ||||
-rw-r--r-- | sim/mn10200/interp.c | 820 | ||||
-rw-r--r-- | sim/mn10200/mn10200_sim.h | 297 | ||||
-rw-r--r-- | sim/mn10200/simops.c | 2449 |
10 files changed, 0 insertions, 8451 deletions
diff --git a/sim/mn10200/ChangeLog b/sim/mn10200/ChangeLog deleted file mode 100644 index ea930dc..0000000 --- a/sim/mn10200/ChangeLog +++ /dev/null @@ -1,472 +0,0 @@ -2004-06-28 Andrew Cagney <cagney@gnu.org> - - * interp.c: Rename ui_loop_hook to deprecated_ui_loop_hook. - -2003-02-27 Andrew Cagney <cagney@redhat.com> - - * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. - -2002-06-16 Andrew Cagney <ac131313@redhat.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -2002-06-09 Andrew Cagney <cagney@redhat.com> - - * Makefile.in (INCLUDE): Update path to callback.h. - * mn10200_sim.h: Include "gdb/callback.h" and "gdb/remote-sim.h". - -2001-04-15 J.T. Conklin <jtc@redback.com> - - * Makefile.in (simops.o): Add simops.h to dependency list. - -Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -1999-05-08 Felix Lee <flee@cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -1999-04-06 Keith Seitz <keiths@cygnus.com> - - * interp.c (sim_stop): Set the sim's exception - to SIGINT. - -1999-04-02 Keith Seitz <keiths@cygnus.com> - - * interp.c (UI_LOOP_POLL_INTERVAL): Define. Used to tweak the - frequency at which ui_loop_hook is called. - (ui_loop_hook_counter): New global defined when NEED_UI_LOOP_HOOK - is defined. - (sim_resume): Call ui_loop_hook (if defined) when the interval - passes. - * Makefile.in (SIM_EXTRA_CFLAGS): Include NEED_UI_LOOP_HOOK. - -Wed Jun 17 11:37:59 1998 Mark Alexander <marka@cygnus.com> - - * Makefile.in: Define NL_TARGET so that targ-vals.h will be used - instead of syscall.h. - * simops.c: Use targ-vals.h instead of syscall.h. - -Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Sun Apr 26 15:19:58 1998 Tom Tromey <tromey@cygnus.com> - - * acconfig.h: New file. - * configure.in: Reverted change of Apr 24; use sinclude again. - -Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Fri Apr 24 11:19:13 1998 Tom Tromey <tromey@cygnus.com> - - * configure.in: Don't call sinclude. - -Thu Apr 23 09:48:14 1998 Tom Tromey <tromey@creche> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Tue Feb 17 12:46:22 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_store_register, sim_fetch_register): Pass in - length parameter. Return -1. - -Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Tue Jan 13 00:01:40 1998 Jeffrey A Law (law@cygnus.com) - - * simops.c: Stores to abs16 memory addresses zero extend the - abs16 address. - -Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Oct 22 14:43:00 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_load): Pass lma_p and sim_write args to - sim_load_file. - -Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Tue Sep 2 18:41:23 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: PC relative instructions are relative to the next - instruction, not the current instruction. - -Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Tue Aug 26 10:40:45 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_kill): Delete. - (sim_create_inferior): Add ABFD argument. - (sim_load): Move setting of PC from here. - (sim_create_inferior): To here. - -Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Mon Aug 25 16:14:44 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_open): Add ABFD argument. - -Tue Jun 24 13:44:08 1997 Jeffrey A Law (law@cygnus.com) - - * interp.c (sim_resume): Clear State.exited. - (sim_stop_reason): If State.exited is nonzero, then indicate that - the simulator exited instead of stopped. - * mn10200_sim.h (struct _state): Add exited field. - * simops.c (syscall): Set State.exited for SYS_exit. - -Tue May 20 17:45:47 1997 Jeffrey A Law (law@cygnus.com) - - * interp.c: Replace all references to load_mem and store_mem - with references to load_byte, load_half, load_3_byte, load_word - and store_byte, store_half, store_3_byte, store_word. - (INLINE): Delete definition. - (load_mem_big): Likewise. - (max_mem): Make it global. - (dispatch): Make this function inline. - (load_mem, store_mem): Delete functions. - * mn10200_sim.h (INLINE): Define. - (RLW): Delete unused definition. - (load_mem, store_mem): Delete declarations. - (load_mem_big): New definition. - (load_byte, load_half, load_3_byte, load_word): New functions. - (store_byte, store_half, store_3_byte, store_word): New functions. - * simops.c: Replace all references to load_mem and store_mem - with references to load_byte, load_half, load_3_byte, load_word - and store_byte, store_half, store_3_byte, store_word. - -Tue May 20 10:21:00 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_open): Add callback argument. - (sim_set_callbacks): Delete SIM_DESC argument. - -Sun May 18 16:59:09 1997 Jeffrey A Law (law@cygnus.com) - - * interp.c (compare_simops): New function. - (sim_open): Sort the Simops table before inserting entries - into the hash table. - -Fri May 16 16:29:18 1997 Jeffrey A Law (law@cygnus.com) - - * interp.c (load_mem): Fix formatting/indention problems with - last change. If we get a load from an out of range address, - abort instead of returning zero. - (store_mem): Abort if we try to store to an out of range address. - -Wed May 14 21:21:30 1997 Bob Manson <manson@charmed.cygnus.com> - - * simops.c (OP_F010): Fix some arguments to correspond - with reality (types of arguments passed to lseek, read, - write, open). - - * interp.c (max_mem): New variable. - (load_mem): Check memory address against max_mem to - avoid some self-destructive behaviors. - -Tue May 13 21:45:24 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Fix typo in cc0 setting for lsr. - -Tue May 6 13:22:12 1997 Jeffrey A Law (law@cygnus.com) - - * interp.c: Random typo/thinko cleanups. - -Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Apr 21 10:29:30 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Fix typo in "open" syscall emulation. - -Fri Apr 18 14:04:31 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_stop): Add stub function. - -Thu Apr 17 03:23:58 1997 Doug Evans <dje@canuck.cygnus.com> - - * Makefile.in (SIM_OBJS): Add sim-load.o. - * interp.c (sim_kind, myname): New static locals. - (sim_open): Set sim_kind, myname. Ignore -E arg. - (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to - load file into simulator. Set start address from bfd. - (sim_create_inferior): Return SIM_RC. Delete arg start_address. - -Wed Apr 16 18:06:50 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * simops.c (OP_F010): SYS_execv, SYS_time, SYS_times, SYS_utime - only include if implemented by host. - -Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Fri Apr 4 20:01:56 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in: Change mn10200-opc.o to m10200-opc.o, to match - corresponding change in opcodes directory. - -Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> - - * interp.c (sim_open): New arg `kind'. - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Thu Mar 20 20:28:14 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200_sim.h: Protect uses of "signed" to cater to broken - non-ansi compilers (HPs). Don't use #error for the same reason. - -Tue Mar 18 12:23:31 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Don't sign-extend immediate for "mov imm16,an". - Simplify "sub" handling. Fix "mul" to properly sign extend - operands. Set CF appropriately for btst imm16,dn. Implement "rti". - - * gencode.c: Delete unused "Opcodes" and "curop" variables. - -Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> - - * configure: Re-generate. - -Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> - - * configure: Regenerate to track ../common/aclocal.m4 changes. - -Thu Mar 13 12:53:14 1997 Doug Evans <dje@canuck.cygnus.com> - - * interp.c (sim_open): New SIM_DESC result. Argument is now - in argv form. - (other sim_*): New SIM_DESC argument. - -Wed Mar 12 15:02:35 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Fix typo for "bclr". - -Wed Feb 26 16:46:13 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Handle new calling convention in emulated syscall - code. - -Mon Feb 24 14:25:11 1997 Jeffrey A Law (law@cygnus.com) - - * interp.c (load_mem_big): Add some missing parens. - -Wed Feb 19 23:19:08 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Don't use "long long" data types for intermediate - values in "divu", "mul" and "mulu" instructions. - -Fri Feb 14 02:46:46 1997 Jeffrey A Law (law@cygnus.com) - - * interp.c (hash): Rework to be more efficient. - (dispatch): Renamed from lookup_hash. Dispatch to the target - function and update the PC here. - (load_mem_big): Now a macro. - (sim_resume): Restructure code to read an insn, determine its - length, call dispatch routines, etc to be much more efficient. - -Fri Feb 7 12:59:36 1997 Jeffrey A Law (law@cygnus.com) - - * interp.c (MAX_HASH): Redefine to 127. - (struct hash_entry): Add "count" field when HASH_STAT is defined. - (hash): Improve hashing for many heavily used opcodes. - (lookup_hash): Bump counters if HASH_STAT is defined. - (sim_open): Don't put the same opcode in the hash table more - than once. Clear counters if HASH_STAT is defined. - (sim_resume): After program exits, dump hash table stats if - HASH_STAT is defined. - -Wed Feb 5 10:28:37 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Fix register extraction for "ext dn". - -Tue Feb 4 17:27:41 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Fix register extractions for "movbu (an), dm". - -Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> - - * Makefile.in (@COMMON_MAKEFILE_FRAG): Use - COMMON_{PRE,POST}_CONFIG_FRAG instead. - * configure.in: sinclude ../common/aclocal.m4. - * configure: Regenerated. - -Fri Jan 31 01:19:02 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Get carry-in bit right for rol. Just clear the - NF flag for btst imm8,dn. - -Wed Jan 29 15:47:42 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Properly compute ZF flag for many insns. - -Sat Jan 25 17:06:55 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Properly truncate divisor and dividend before - performing "divu" operation. - -Fri Jan 24 10:47:48 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c (init_system): Allocate 2^19 bytes of space for - the simulator. - -Thu Jan 23 21:17:33 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Rework code to extract arguments for emulated - syscalls to handle 24bit pointers. - -Thu Jan 23 14:06:04 1997 Stu Grossman (grossman@critters.cygnus.com) - - * configure configure.in Makefile.in: Update to new configure - scheme which is more compatible with WinGDB builds. - * configure.in: Improve comment on how to run autoconf. - * configure: Re-run autoconf to get new ../common/aclocal.m4. - * Makefile.in: Use autoconf substitution to install common - makefile fragment. - -Thu Jan 23 12:04:38 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Fix destination register for "mov (abs24),an". - -Tue Jan 21 15:59:21 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: "rts" adds 4 to the stack pointer. - - * simops.c: Fix CF and CX computation for add instructions. - - * simops.c: Leave the upper 8 bits alone for logical ops. - Mask off high 8 bits before doing any shifts/rotates. - Fix carry bit handling in rotates again. - -Mon Jan 20 10:45:08 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Don't lose the sign bit for "asr". - -Fri Jan 17 01:45:14 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Fix overflow computation for "cmp" and "sub" - instructions. - - * simops.c: Use the right register for "jmp (an)" and "jsr (an)". - - * interp.c (hash): Improve hashing for 3 byte instructions. - - * simops.c: Fix extraction of 16/24bit immediates for some - instructions. "cmp" instructions only modify the PSW. - Fix various thinkos when extracting register operands too. - -Thu Jan 16 07:47:56 1997 Jeffrey A Law (law@cygnus.com) - - * simops.c: Fix "rol" and "ror". - - * simops.c: Truncate PC to 24bits after modifying it. - Closer stab at emulated system calls. - -Tue Jan 14 12:33:12 1997 Jeffrey A Law (law@cygnus.com) - - * interp.c (hash): Improve hashing of two byte insns. - (store_mem): Handle storing 3 byte quantities. - - * simops.c: Fix various typos/thinkos. - - * interp.c (load_mem_big, load_mem, store_mem): Fix thinko in - code to handle 24bit addresses. - * simops.c (REG0_8, REG0_16): Fix typo. - -Mon Jan 6 16:17:09 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200_sim.h: Various fixes for mixed 16/24bit architecture. - * interp.c: Similarly. - * simops.c: Similarly. - - * Makefile.in, config.in, configure, configure.in: New files. - * gencode.c, interp.c, mn10200_sim.h, simops.c: New files. - diff --git a/sim/mn10200/Makefile.in b/sim/mn10200/Makefile.in deleted file mode 100644 index 563a4ed..0000000 --- a/sim/mn10200/Makefile.in +++ /dev/null @@ -1,52 +0,0 @@ -# Makefile template for Configure for the mn10200 sim library. -# Copyright (C) 1997 Free Software Foundation, Inc. -# Written by Cygnus Support. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - -## COMMON_PRE_CONFIG_FRAG - -SIM_OBJS = interp.o table.o simops.o sim-load.o -SIM_EXTRA_CFLAGS = -I$(srcdir)/../../newlib/libc/sys/sysmec -DNEED_UI_LOOP_HOOK -SIM_EXTRA_CLEAN = clean-extra - -# Select mn10200 support in nltvals.def. -NL_TARGET = -DNL_TARGET_mn10200 - -INCLUDE = mn10200_sim.h $(srcdir)/../../include/gdb/callback.h - -## COMMON_POST_CONFIG_FRAG - -simops.h: gencode - ./gencode -h >$@ - -table.c: gencode simops.h - ./gencode >$@ - -gencode.o: gencode.c $(INCLUDE) - $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/gencode.c - -m10200-opc.o: $(srcdir)/../../opcodes/m10200-opc.c - $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/../../opcodes/m10200-opc.c - -gencode: gencode.o m10200-opc.o - $(CC_FOR_BUILD) $(BUILD_CFLAGS) -o gencode gencode.o m10200-opc.o $(BUILD_LIB) - -clean-extra: - rm -f table.c simops.h gencode - -interp.o: interp.c table.c $(INCLUDE) -simops.o: simops.c simops.h $(INCLUDE) -table.o: table.c diff --git a/sim/mn10200/acconfig.h b/sim/mn10200/acconfig.h deleted file mode 100644 index f9b87a1..0000000 --- a/sim/mn10200/acconfig.h +++ /dev/null @@ -1,15 +0,0 @@ - -/* Define to 1 if NLS is requested. */ -#undef ENABLE_NLS - -/* Define as 1 if you have catgets and don't want to use GNU gettext. */ -#undef HAVE_CATGETS - -/* Define as 1 if you have gettext and don't want to use GNU gettext. */ -#undef HAVE_GETTEXT - -/* Define as 1 if you have the stpcpy function. */ -#undef HAVE_STPCPY - -/* Define if your locale.h file contains LC_MESSAGES. */ -#undef HAVE_LC_MESSAGES diff --git a/sim/mn10200/config.in b/sim/mn10200/config.in deleted file mode 100644 index 1f87a2b..0000000 --- a/sim/mn10200/config.in +++ /dev/null @@ -1,158 +0,0 @@ -/* config.in. Generated automatically from configure.in by autoheader. */ - -/* Define if using alloca.c. */ -#undef C_ALLOCA - -/* Define to empty if the keyword does not work. */ -#undef const - -/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. - This function is required for alloca.c support on those systems. */ -#undef CRAY_STACKSEG_END - -/* Define if you have alloca, as a function or macro. */ -#undef HAVE_ALLOCA - -/* Define if you have <alloca.h> and it should be used (not on Ultrix). */ -#undef HAVE_ALLOCA_H - -/* Define if you have a working `mmap' system call. */ -#undef HAVE_MMAP - -/* Define as __inline if that's what the C compiler calls it. */ -#undef inline - -/* Define to `long' if <sys/types.h> doesn't define. */ -#undef off_t - -/* Define if you need to in order for stat and other things to work. */ -#undef _POSIX_SOURCE - -/* Define as the return type of signal handlers (int or void). */ -#undef RETSIGTYPE - -/* Define to `unsigned' if <sys/types.h> doesn't define. */ -#undef size_t - -/* If using the C implementation of alloca, define if you know the - direction of stack growth for your system; otherwise it will be - automatically deduced at run-time. - STACK_DIRECTION > 0 => grows toward higher addresses - STACK_DIRECTION < 0 => grows toward lower addresses - STACK_DIRECTION = 0 => direction of growth unknown - */ -#undef STACK_DIRECTION - -/* Define if you have the ANSI C header files. */ -#undef STDC_HEADERS - -/* Define to 1 if NLS is requested. */ -#undef ENABLE_NLS - -/* Define as 1 if you have gettext and don't want to use GNU gettext. */ -#undef HAVE_GETTEXT - -/* Define as 1 if you have the stpcpy function. */ -#undef HAVE_STPCPY - -/* Define if your locale.h file contains LC_MESSAGES. */ -#undef HAVE_LC_MESSAGES - -/* Define if you have the __argz_count function. */ -#undef HAVE___ARGZ_COUNT - -/* Define if you have the __argz_next function. */ -#undef HAVE___ARGZ_NEXT - -/* Define if you have the __argz_stringify function. */ -#undef HAVE___ARGZ_STRINGIFY - -/* Define if you have the __setfpucw function. */ -#undef HAVE___SETFPUCW - -/* Define if you have the dcgettext function. */ -#undef HAVE_DCGETTEXT - -/* Define if you have the getcwd function. */ -#undef HAVE_GETCWD - -/* Define if you have the getpagesize function. */ -#undef HAVE_GETPAGESIZE - -/* Define if you have the getrusage function. */ -#undef HAVE_GETRUSAGE - -/* Define if you have the munmap function. */ -#undef HAVE_MUNMAP - -/* Define if you have the putenv function. */ -#undef HAVE_PUTENV - -/* Define if you have the setenv function. */ -#undef HAVE_SETENV - -/* Define if you have the setlocale function. */ -#undef HAVE_SETLOCALE - -/* Define if you have the sigaction function. */ -#undef HAVE_SIGACTION - -/* Define if you have the stpcpy function. */ -#undef HAVE_STPCPY - -/* Define if you have the strcasecmp function. */ -#undef HAVE_STRCASECMP - -/* Define if you have the strchr function. */ -#undef HAVE_STRCHR - -/* Define if you have the time function. */ -#undef HAVE_TIME - -/* Define if you have the <argz.h> header file. */ -#undef HAVE_ARGZ_H - -/* Define if you have the <fcntl.h> header file. */ -#undef HAVE_FCNTL_H - -/* Define if you have the <fpu_control.h> header file. */ -#undef HAVE_FPU_CONTROL_H - -/* Define if you have the <limits.h> header file. */ -#undef HAVE_LIMITS_H - -/* Define if you have the <locale.h> header file. */ -#undef HAVE_LOCALE_H - -/* Define if you have the <malloc.h> header file. */ -#undef HAVE_MALLOC_H - -/* Define if you have the <nl_types.h> header file. */ -#undef HAVE_NL_TYPES_H - -/* Define if you have the <stdlib.h> header file. */ -#undef HAVE_STDLIB_H - -/* Define if you have the <string.h> header file. */ -#undef HAVE_STRING_H - -/* Define if you have the <strings.h> header file. */ -#undef HAVE_STRINGS_H - -/* Define if you have the <sys/param.h> header file. */ -#undef HAVE_SYS_PARAM_H - -/* Define if you have the <sys/resource.h> header file. */ -#undef HAVE_SYS_RESOURCE_H - -/* Define if you have the <sys/time.h> header file. */ -#undef HAVE_SYS_TIME_H - -/* Define if you have the <time.h> header file. */ -#undef HAVE_TIME_H - -/* Define if you have the <unistd.h> header file. */ -#undef HAVE_UNISTD_H - -/* Define if you have the <values.h> header file. */ -#undef HAVE_VALUES_H diff --git a/sim/mn10200/configure b/sim/mn10200/configure deleted file mode 100755 index 2720d6b..0000000 --- a/sim/mn10200/configure +++ /dev/null @@ -1,4024 +0,0 @@ -#! /bin/sh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -sim_inline="-DDEFAULT_INLINE=0" - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# This file is derived from `gettext.m4'. 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Not all systems have dirname. - ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` - if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then - # The file is in a subdirectory. - test ! -d "$ac_dir" && mkdir "$ac_dir" - fi - rm -f $ac_file - mv conftest.h $ac_file - fi -fi; done - -EOF - -cat >> $CONFIG_STATUS <<EOF -ac_sources="$sim_link_files" -ac_dests="$sim_link_links" -EOF - -cat >> $CONFIG_STATUS <<\EOF -srcdir=$ac_given_srcdir -while test -n "$ac_sources"; do - set $ac_dests; ac_dest=$1; shift; ac_dests=$* - set $ac_sources; ac_source=$1; shift; ac_sources=$* - - echo "linking $srcdir/$ac_source to $ac_dest" - - if test ! -r $srcdir/$ac_source; then - { echo "configure: error: $srcdir/$ac_source: File not found" 1>&2; exit 1; } - fi - rm -f $ac_dest - - # Make relative symlinks. - # Remove last slash and all that follows it. Not all systems have dirname. - ac_dest_dir=`echo $ac_dest|sed 's%/[^/][^/]*$%%'` - if test "$ac_dest_dir" != "$ac_dest" && test "$ac_dest_dir" != .; then - # The dest file is in a subdirectory. - test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir" - ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`" - # A "../" for each directory in $ac_dest_dir_suffix. - ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'` - else - ac_dest_dir_suffix= ac_dots= - fi - - case "$srcdir" in - [/$]*) ac_rel_source="$srcdir/$ac_source" ;; - *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;; - esac - - # Make a symlink if possible; otherwise try a hard link. - if ln -s $ac_rel_source $ac_dest 2>/dev/null || - ln $srcdir/$ac_source $ac_dest; then : - else - { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; } - fi -done -EOF -cat >> $CONFIG_STATUS <<EOF - -EOF -cat >> $CONFIG_STATUS <<\EOF -case "x$CONFIG_FILES" in - xMakefile*) - echo "Merging Makefile.sim+Make-common.sim into Makefile ..." - rm -f Makesim1.tmp Makesim2.tmp Makefile - sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp - sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp - sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \ - -e '/^## COMMON_POST_/ r Makesim2.tmp' \ - <Makefile.sim >Makefile - rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp - ;; - esac - case "x$CONFIG_HEADERS" in xconfig.h:config.in) echo > stamp-h ;; esac - -exit 0 -EOF -chmod +x $CONFIG_STATUS -rm -fr confdefs* $ac_clean_files -test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 - - diff --git a/sim/mn10200/configure.in b/sim/mn10200/configure.in deleted file mode 100644 index 033b0bc..0000000 --- a/sim/mn10200/configure.in +++ /dev/null @@ -1,10 +0,0 @@ -dnl Process this file with autoconf to produce a configure script. -sinclude(../common/aclocal.m4) -AC_PREREQ(2.5)dnl -AC_INIT(Makefile.in) - -SIM_AC_COMMON - -AC_CHECK_HEADERS(unistd.h) - -SIM_AC_OUTPUT diff --git a/sim/mn10200/gencode.c b/sim/mn10200/gencode.c deleted file mode 100644 index 8ba873e..0000000 --- a/sim/mn10200/gencode.c +++ /dev/null @@ -1,154 +0,0 @@ -#include "mn10200_sim.h" - -static void write_header PARAMS ((void)); -static void write_opcodes PARAMS ((void)); -static void write_template PARAMS ((void)); - -int -main (argc, argv) - int argc; - char *argv[]; -{ - if ((argc > 1) && (strcmp (argv[1], "-h") == 0)) - write_header(); - else if ((argc > 1) && (strcmp (argv[1], "-t") == 0)) - write_template (); - else - write_opcodes(); - return 0; -} - - -static void -write_header () -{ - struct mn10200_opcode *opcode; - - for (opcode = (struct mn10200_opcode *)mn10200_opcodes; opcode->name; opcode++) - printf("void OP_%X PARAMS ((unsigned long, unsigned long));\t\t/* %s */\n", - opcode->opcode, opcode->name); -} - - -/* write_template creates a file all required functions, ready */ -/* to be filled out */ - -static void -write_template () -{ - struct mn10200_opcode *opcode; - int i,j; - - printf ("#include \"mn10200_sim.h\"\n"); - printf ("#include \"simops.h\"\n"); - - for (opcode = (struct mn10200_opcode *)mn10200_opcodes; opcode->name; opcode++) - { - printf("/* %s */\nvoid\nOP_%X (insn, extension)\n unsigned long insn, extension;\n{\n", opcode->name, opcode->opcode); - - /* count operands */ - j = 0; - for (i = 0; i < 6; i++) - { - int flags = mn10200_operands[opcode->operands[i]].flags; - - if (flags) - j++; - } - switch (j) - { - case 0: - printf ("printf(\" %s\\n\");\n", opcode->name); - break; - case 1: - printf ("printf(\" %s\\t%%x\\n\", OP[0]);\n", opcode->name); - break; - case 2: - printf ("printf(\" %s\\t%%x,%%x\\n\",OP[0],OP[1]);\n", - opcode->name); - break; - case 3: - printf ("printf(\" %s\\t%%x,%%x,%%x\\n\",OP[0],OP[1],OP[2]);\n", - opcode->name); - break; - default: - fprintf (stderr,"Too many operands: %d\n", j); - } - printf ("}\n\n"); - } -} - -static void -write_opcodes () -{ - struct mn10200_opcode *opcode; - int i, j; - int numops; - - /* write out opcode table */ - printf ("#include \"mn10200_sim.h\"\n"); - printf ("#include \"simops.h\"\n\n"); - printf ("struct simops Simops[] = {\n"); - - for (opcode = (struct mn10200_opcode *)mn10200_opcodes; opcode->name; opcode++) - { - int size; - - if (opcode->format == FMT_1) - size = 1; - else if (opcode->format == FMT_2 || opcode->format == FMT_4) - size = 2; - else if (opcode->format == FMT_3 || opcode->format == FMT_5) - size = 3; - else if (opcode->format == FMT_6) - size = 4; - else if (opcode->format == FMT_7) - size = 5; - else - abort (); - - printf (" { 0x%x,0x%x,OP_%X,%d,%d,", - opcode->opcode, opcode->mask, opcode->opcode, - size, opcode->format); - - /* count operands */ - j = 0; - for (i = 0; i < 6; i++) - { - int flags = mn10200_operands[opcode->operands[i]].flags; - - if (flags) - j++; - } - printf ("%d,{",j); - - j = 0; - numops = 0; - for (i = 0; i < 6; i++) - { - int flags = mn10200_operands[opcode->operands[i]].flags; - int shift = mn10200_operands[opcode->operands[i]].shift; - - if (flags) - { - if (j) - printf (", "); - printf ("%d,%d,%d", shift, - mn10200_operands[opcode->operands[i]].bits,flags); - j = 1; - numops++; - } - } - - switch (numops) - { - case 0: - printf ("0,0,0"); - case 1: - printf (",0,0,0"); - } - - printf ("}},\n"); - } - printf ("{ 0,0,NULL,0,0,0,{0,0,0,0,0,0}},\n};\n"); -} diff --git a/sim/mn10200/interp.c b/sim/mn10200/interp.c deleted file mode 100644 index 90529c8..0000000 --- a/sim/mn10200/interp.c +++ /dev/null @@ -1,820 +0,0 @@ -#include <signal.h> -#include "sysdep.h" -#include "bfd.h" - -#include "mn10200_sim.h" - -#ifdef NEED_UI_LOOP_HOOK -/* How often to run the ui_loop update, when in use */ -#define UI_LOOP_POLL_INTERVAL 0x60000 - -/* Counter for the ui_loop_hook update */ -static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; - -/* Actual hook to call to run through gdb's gui event loop */ -extern int (*deprecated_ui_loop_hook) (int); -#endif /* NEED_UI_LOOP_HOOK */ - -host_callback *mn10200_callback; -int mn10200_debug; -static SIM_OPEN_KIND sim_kind; -static char *myname; - -static void dispatch PARAMS ((uint32, uint32, int)); -static long hash PARAMS ((long)); -static void init_system PARAMS ((void)); -#define MAX_HASH 127 - -struct hash_entry -{ - struct hash_entry *next; - long opcode; - long mask; - struct simops *ops; -#ifdef HASH_STAT - unsigned long count; -#endif -}; - -int max_mem = 0; -struct hash_entry hash_table[MAX_HASH+1]; - - -/* This probably doesn't do a very good job at bucket filling, but - it's simple... */ -static INLINE long -hash(insn) - long insn; -{ - /* These are one byte insns. */ - if ((insn & 0xffffff00) == 0x00) - { - if ((insn & 0xf0) != 0x80) - return ((insn & 0xf0) >> 4) & 0x7f; - - if ((insn & 0xf0) == 0x80 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - return (insn & 0xf0) & 0x7f; - - return (insn & 0xff) & 0x7f; - } - - if ((insn & 0xffff0000) == 0) - { - if ((insn & 0xf000) == 0xd000) - return ((insn & 0xfc00) >> 10) & 0x7f; - - if ((insn & 0xf000) == 0xe000) - return ((insn & 0xff00) >> 8) & 0x7f; - - if ((insn & 0xf200) == 0xf200) - return ((insn & 0xfff0) >> 4) & 0x7f; - - if ((insn & 0xc000) == 0x4000 - || (insn & 0xf000) == 0x8000) - return ((insn & 0xf000) >> 8) & 0x7f; - - if ((insn & 0xf200) == 0xf000) - return ((insn & 0xffc0) >> 8) & 0x7f; - - return ((insn & 0xff00) >> 8) & 0x7f; - } - - if ((insn & 0xff000000) == 0) - { - - if ((insn & 0xf00000) != 0xf00000 - || (insn & 0xfc0000) == 0xf80000) - return ((insn & 0xfc0000) >> 16) & 0x7f; - - if ((insn & 0xff0000) == 0xf50000) - return ((insn & 0xfff000) >> 12) & 0x7f; - return ((insn & 0xff0000) >> 16) & 0x7f; - } - - return ((insn & 0xfff0000) >> 20) & 0x7f; -} - -static INLINE void -dispatch (insn, extension, length) - uint32 insn; - uint32 extension; - int length; -{ - struct hash_entry *h; - - h = &hash_table[hash(insn)]; - - while ((insn & h->mask) != h->opcode - || (length != h->ops->length)) - { - if (!h->next) - { - (*mn10200_callback->printf_filtered) (mn10200_callback, - "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC); - exit(1); - } - h = h->next; - } - - -#ifdef HASH_STAT - h->count++; -#endif - - /* Now call the right function. */ - (h->ops->func)(insn, extension); - PC += length; -} - -/* FIXME These would more efficient to use than load_mem/store_mem, - but need to be changed to use the memory map. */ - -uint32 -get_word (x) - uint8 *x; -{ - uint8 *a = x; - return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]); -} - -void -put_word (addr, data) - uint8 *addr; - uint32 data; -{ - uint8 *a = addr; - a[0] = data & 0xff; - a[1] = (data >> 8) & 0xff; - a[2] = (data >> 16) & 0xff; - a[3] = (data >> 24) & 0xff; -} - -void -sim_size (power) - int power; - -{ - if (State.mem) - free (State.mem); - - max_mem = 1 << power; - State.mem = (uint8 *) calloc (1, 1 << power); - if (!State.mem) - { - (*mn10200_callback->printf_filtered) (mn10200_callback, "Allocation of main memory failed.\n"); - exit (1); - } -} - -static void -init_system () -{ - if (!State.mem) - sim_size(19); -} - -int -sim_write (sd,addr, buffer, size) - SIM_DESC sd; - SIM_ADDR addr; - unsigned char *buffer; - int size; -{ - int i; - - init_system (); - - for (i = 0; i < size; i++) - store_byte (addr + i, buffer[i]); - - return size; -} - -/* Compare two opcode table entries for qsort. */ -static int -compare_simops (arg1, arg2) - const PTR arg1; - const PTR arg2; -{ - unsigned long code1 = ((struct simops *)arg1)->opcode; - unsigned long code2 = ((struct simops *)arg2)->opcode; - - if (code1 < code2) - return -1; - if (code2 < code1) - return 1; - return 0; -} - -SIM_DESC -sim_open (kind, cb, abfd, argv) - SIM_OPEN_KIND kind; - host_callback *cb; - struct bfd *abfd; - char **argv; -{ - struct simops *s; - struct hash_entry *h; - char **p; - int i; - - mn10200_callback = cb; - - /* Sort the opcode array from smallest opcode to largest. - This will generally improve simulator performance as the smaller - opcodes are generally preferred to the larger opcodes. */ - for (i = 0, s = Simops; s->func; s++, i++) - ; - qsort (Simops, i, sizeof (Simops[0]), compare_simops); - - sim_kind = kind; - myname = argv[0]; - - for (p = argv + 1; *p; ++p) - { - if (strcmp (*p, "-E") == 0) - ++p; /* ignore endian spec */ - else -#ifdef DEBUG - if (strcmp (*p, "-t") == 0) - mn10200_debug = DEBUG; - else -#endif - (*mn10200_callback->printf_filtered) (mn10200_callback, "ERROR: unsupported option(s): %s\n",*p); - } - - /* put all the opcodes in the hash table */ - for (s = Simops; s->func; s++) - { - h = &hash_table[hash(s->opcode)]; - - /* go to the last entry in the chain */ - while (h->next) - { - /* Don't insert the same opcode more than once. */ - if (h->opcode == s->opcode - && h->mask == s->mask - && h->ops == s) - break; - else - h = h->next; - } - - /* Don't insert the same opcode more than once. */ - if (h->opcode == s->opcode - && h->mask == s->mask - && h->ops == s) - continue; - - if (h->ops) - { - h->next = calloc(1,sizeof(struct hash_entry)); - h = h->next; - } - h->ops = s; - h->mask = s->mask; - h->opcode = s->opcode; -#ifdef HASH_STAT - h->count = 0; -#endif - } - - /* fudge our descriptor for now */ - return (SIM_DESC) 1; -} - - -void -sim_set_profile (n) - int n; -{ - (*mn10200_callback->printf_filtered) (mn10200_callback, "sim_set_profile %d\n", n); -} - -void -sim_set_profile_size (n) - int n; -{ - (*mn10200_callback->printf_filtered) (mn10200_callback, "sim_set_profile_size %d\n", n); -} - -int -sim_stop (sd) - SIM_DESC sd; -{ - State.exception = SIGINT; - return 1; -} - -void -sim_resume (sd, step, siggnal) - SIM_DESC sd; - int step, siggnal; -{ - uint32 inst; - - if (step) - State.exception = SIGTRAP; - else - State.exception = 0; - - State.exited = 0; - - do - { - unsigned long insn, extension; - -#ifdef NEED_UI_LOOP_HOOK - if (deprecated_ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) - { - ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; - deprecated_ui_loop_hook (0); - } -#endif /* NEED_UI_LOOP_HOOK */ - - /* Fetch the current instruction, fetch a double word to - avoid redundant fetching for the common cases below. */ - inst = load_mem_big (PC, 2); - - /* Using a giant case statement may seem like a waste because of the - code/rodata size the table itself will consume. However, using - a giant case statement speeds up the simulator by 10-15% by avoiding - cascading if/else statements or cascading case statements. */ - switch ((inst >> 8) & 0xff) - { - /* All the single byte insns except 0x80, which must - be handled specially. */ - case 0x00: - case 0x01: - case 0x02: - case 0x03: - case 0x04: - case 0x05: - case 0x06: - case 0x07: - case 0x08: - case 0x09: - case 0x0a: - case 0x0b: - case 0x0c: - case 0x0d: - case 0x0e: - case 0x0f: - case 0x10: - case 0x11: - case 0x12: - case 0x13: - case 0x14: - case 0x15: - case 0x16: - case 0x17: - case 0x18: - case 0x19: - case 0x1a: - case 0x1b: - case 0x1c: - case 0x1d: - case 0x1e: - case 0x1f: - case 0x20: - case 0x21: - case 0x22: - case 0x23: - case 0x24: - case 0x25: - case 0x26: - case 0x27: - case 0x28: - case 0x29: - case 0x2a: - case 0x2b: - case 0x2c: - case 0x2d: - case 0x2e: - case 0x2f: - case 0x30: - case 0x31: - case 0x32: - case 0x33: - case 0x34: - case 0x35: - case 0x36: - case 0x37: - case 0x38: - case 0x39: - case 0x3a: - case 0x3b: - case 0x3c: - case 0x3d: - case 0x3e: - case 0x3f: - case 0x90: - case 0x91: - case 0x92: - case 0x93: - case 0x94: - case 0x95: - case 0x96: - case 0x97: - case 0x98: - case 0x99: - case 0x9a: - case 0x9b: - case 0x9c: - case 0x9d: - case 0x9e: - case 0x9f: - case 0xa0: - case 0xa1: - case 0xa2: - case 0xa3: - case 0xa4: - case 0xa5: - case 0xa6: - case 0xa7: - case 0xa8: - case 0xa9: - case 0xaa: - case 0xab: - case 0xac: - case 0xad: - case 0xae: - case 0xaf: - case 0xb0: - case 0xb1: - case 0xb2: - case 0xb3: - case 0xb4: - case 0xb5: - case 0xb6: - case 0xb7: - case 0xb8: - case 0xb9: - case 0xba: - case 0xbb: - case 0xbc: - case 0xbd: - case 0xbe: - case 0xbf: - case 0xeb: - case 0xf6: - case 0xfe: - case 0xff: - insn = (inst >> 8) & 0xff; - extension = 0; - dispatch (insn, extension, 1); - break; - - /* Special case as mov dX,dX really means mov imm8,dX. */ - case 0x80: - case 0x85: - case 0x8a: - case 0x8f: - /* Fetch the full instruction. */ - insn = inst; - extension = 0; - dispatch (insn, extension, 2); - break; - - case 0x81: - case 0x82: - case 0x83: - case 0x84: - case 0x86: - case 0x87: - case 0x88: - case 0x89: - case 0x8b: - case 0x8c: - case 0x8d: - case 0x8e: - insn = (inst >> 8) & 0xff; - extension = 0; - dispatch (insn, extension, 1); - break; - - /* And the two byte insns. */ - case 0x40: - case 0x41: - case 0x42: - case 0x43: - case 0x44: - case 0x45: - case 0x46: - case 0x47: - case 0x48: - case 0x49: - case 0x4a: - case 0x4b: - case 0x4c: - case 0x4d: - case 0x4e: - case 0x4f: - case 0x50: - case 0x51: - case 0x52: - case 0x53: - case 0x54: - case 0x55: - case 0x56: - case 0x57: - case 0x58: - case 0x59: - case 0x5a: - case 0x5b: - case 0x5c: - case 0x5d: - case 0x5e: - case 0x5f: - case 0x60: - case 0x61: - case 0x62: - case 0x63: - case 0x64: - case 0x65: - case 0x66: - case 0x67: - case 0x68: - case 0x69: - case 0x6a: - case 0x6b: - case 0x6c: - case 0x6d: - case 0x6e: - case 0x6f: - case 0x70: - case 0x71: - case 0x72: - case 0x73: - case 0x74: - case 0x75: - case 0x76: - case 0x77: - case 0x78: - case 0x79: - case 0x7a: - case 0x7b: - case 0x7c: - case 0x7d: - case 0x7e: - case 0x7f: - case 0xd0: - case 0xd1: - case 0xd2: - case 0xd3: - case 0xd4: - case 0xd5: - case 0xd6: - case 0xd7: - case 0xd8: - case 0xd9: - case 0xda: - case 0xdb: - case 0xe0: - case 0xe1: - case 0xe2: - case 0xe3: - case 0xe4: - case 0xe5: - case 0xe6: - case 0xe7: - case 0xe8: - case 0xe9: - case 0xea: - case 0xf0: - case 0xf1: - case 0xf2: - case 0xf3: - /* Fetch the full instruction. */ - insn = inst; - extension = 0; - dispatch (insn, extension, 2); - break; - - /* And the 3 byte insns with a 16bit operand in little - endian format. */ - case 0xc0: - case 0xc1: - case 0xc2: - case 0xc3: - case 0xc4: - case 0xc5: - case 0xc6: - case 0xc7: - case 0xc8: - case 0xc9: - case 0xca: - case 0xcb: - case 0xcc: - case 0xcd: - case 0xce: - case 0xcf: - case 0xdc: - case 0xdd: - case 0xde: - case 0xdf: - case 0xec: - case 0xed: - case 0xee: - case 0xef: - case 0xf8: - case 0xf9: - case 0xfa: - case 0xfb: - case 0xfc: - case 0xfd: - insn = load_byte (PC); - insn <<= 16; - insn |= load_half (PC + 1); - extension = 0; - dispatch (insn, extension, 3); - break; - - /* 3 byte insns without 16bit operand. */ - case 0xf5: - insn = load_mem_big (PC, 3); - extension = 0; - dispatch (insn, extension, 3); - break; - - /* 4 byte insns. */ - case 0xf7: - insn = inst; - insn <<= 16; - insn |= load_half (PC + 2); - extension = 0; - dispatch (insn, extension, 4); - break; - - case 0xf4: - insn = inst; - insn <<= 16; - insn |= load_mem_big (PC + 4, 1) << 8; - insn |= load_mem_big (PC + 3, 1); - extension = load_mem_big (PC + 2, 1); - dispatch (insn, extension, 5); - break; - - default: - abort (); - } - } - while (!State.exception); - -#ifdef HASH_STAT - { - int i; - for (i = 0; i < MAX_HASH; i++) - { - struct hash_entry *h; - h = &hash_table[i]; - - printf("hash 0x%x:\n", i); - - while (h) - { - printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count); - h = h->next; - } - - printf("\n\n"); - } - fflush (stdout); - } -#endif - -} - - -void -sim_close (sd, quitting) - SIM_DESC sd; - int quitting; -{ - /* nothing to do */ -} - -int -sim_trace (sd) - SIM_DESC sd; -{ -#ifdef DEBUG - mn10200_debug = DEBUG; -#endif - sim_resume (sd, 0, 0); - return 1; -} - -void -sim_info (sd, verbose) - SIM_DESC sd; - int verbose; -{ - (*mn10200_callback->printf_filtered) (mn10200_callback, "sim_info\n"); -} - -SIM_RC -sim_create_inferior (sd, abfd, argv, env) - SIM_DESC sd; - struct bfd *abfd; - char **argv; - char **env; -{ - if (abfd != NULL) - PC = bfd_get_start_address (abfd); - else - PC = 0; - return SIM_RC_OK; -} - -void -sim_set_callbacks (p) - host_callback *p; -{ - mn10200_callback = p; -} - -/* All the code for exiting, signals, etc needs to be revamped. - - This is enough to get c-torture limping though. */ - -void -sim_stop_reason (sd, reason, sigrc) - SIM_DESC sd; - enum sim_stop *reason; - int *sigrc; -{ - if (State.exited) - *reason = sim_exited; - else - *reason = sim_stopped; - if (State.exception == SIGQUIT) - *sigrc = 0; - else - *sigrc = State.exception; -} - -int -sim_fetch_register (sd, rn, memory, length) - SIM_DESC sd; - int rn; - unsigned char *memory; - int length; -{ - put_word (memory, State.regs[rn]); - return -1; -} - -int -sim_store_register (sd, rn, memory, length) - SIM_DESC sd; - int rn; - unsigned char *memory; - int length; -{ - State.regs[rn] = get_word (memory); - return -1; -} - -int -sim_read (sd, addr, buffer, size) - SIM_DESC sd; - SIM_ADDR addr; - unsigned char *buffer; - int size; -{ - int i; - for (i = 0; i < size; i++) - buffer[i] = load_byte (addr + i); - - return size; -} - -void -sim_do_command (sd, cmd) - SIM_DESC sd; - char *cmd; -{ - (*mn10200_callback->printf_filtered) (mn10200_callback, "\"%s\" is not a valid mn10200 simulator command.\n", cmd); -} - -SIM_RC -sim_load (sd, prog, abfd, from_tty) - SIM_DESC sd; - char *prog; - bfd *abfd; - int from_tty; -{ - extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ - bfd *prog_bfd; - - prog_bfd = sim_load_file (sd, myname, mn10200_callback, prog, abfd, - sim_kind == SIM_OPEN_DEBUG, - 0, sim_write); - if (prog_bfd == NULL) - return SIM_RC_FAIL; - if (abfd == NULL) - bfd_close (prog_bfd); - return SIM_RC_OK; -} diff --git a/sim/mn10200/mn10200_sim.h b/sim/mn10200/mn10200_sim.h deleted file mode 100644 index 2f85aa0..0000000 --- a/sim/mn10200/mn10200_sim.h +++ /dev/null @@ -1,297 +0,0 @@ -#include <stdio.h> -#include <ctype.h> -#include "ansidecl.h" -#include "gdb/callback.h" -#include "opcode/mn10200.h" -#include <limits.h> -#include "gdb/remote-sim.h" - -#ifndef INLINE -#ifdef __GNUC__ -#define INLINE inline -#else -#define INLINE -#endif -#endif - -extern host_callback *mn10200_callback; - -#define DEBUG_TRACE 0x00000001 -#define DEBUG_VALUES 0x00000002 - -extern int mn10200_debug; - -#ifdef __STDC__ -#define SIGNED signed -#else -#define SIGNED -#endif - -#if UCHAR_MAX == 255 -typedef unsigned char uint8; -typedef SIGNED char int8; -#else -error "Char is not an 8-bit type" -#endif - -#if SHRT_MAX == 32767 -typedef unsigned short uint16; -typedef SIGNED short int16; -#else -error "Short is not a 16-bit type" -#endif - -#if INT_MAX == 2147483647 - -typedef unsigned int uint32; -typedef SIGNED int int32; - -#else -# if LONG_MAX == 2147483647 - -typedef unsigned long uint32; -typedef SIGNED long int32; - -# else - error "Neither int nor long is a 32-bit type" -# endif -#endif - -typedef uint32 reg_t; - -struct simops -{ - long opcode; - long mask; - void (*func)(); - int length; - int format; - int numops; - int operands[16]; -}; - -/* The current state of the processor; registers, memory, etc. */ - -struct _state -{ - reg_t regs[11]; /* registers, d0-d3, a0-a3, pc, mdr, psw */ - uint8 *mem; /* main memory */ - int exception; /* Actually a signal number. */ - int exited; /* Did the program exit? */ -} State; - -extern uint32 OP[4]; -extern struct simops Simops[]; - -#define PC (State.regs[8]) - -#define PSW (State.regs[10]) -#define PSW_ZF 0x1 -#define PSW_NF 0x2 -#define PSW_CF 0x4 -#define PSW_VF 0x8 -#define PSW_ZX 0x10 -#define PSW_NX 0x20 -#define PSW_CX 0x40 -#define PSW_VX 0x80 - -#define REG_D0 0 -#define REG_A0 4 -#define REG_SP 7 -#define REG_PC 8 -#define REG_MDR 9 -#define REG_PSW 10 - -#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) - -/* sign-extend a 4-bit number */ -#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) - -/* sign-extend a 5-bit number */ -#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) - -/* sign-extend an 8-bit number */ -#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80) - -/* sign-extend a 9-bit number */ -#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) - -/* sign-extend a 16-bit number */ -#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000) - -/* sign-extend a 22-bit number */ -#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000) - -/* sign-extend a 24-bit number */ -#define SEXT24(x) ((((x)&0xffffff)^(~0x7fffff))+0x800000) - -#ifdef _WIN32 -#define SIGTRAP 5 -#define SIGQUIT 3 -#endif - -extern int max_mem; - -#define load_mem_big(addr,len) \ - (len == 1 ? *(((addr) & 0xffffff) + State.mem) : \ - len == 2 ? ((*(((addr) & 0xffffff) + State.mem) << 8) \ - | *((((addr) + 1) & 0xffffff) + State.mem)) : \ - ((*(((addr) & 0xffffff) + State.mem) << 16) \ - | (*((((addr) + 1) & 0xffffff) + State.mem) << 8) \ - | *((((addr) + 2) & 0xffffff) + State.mem))) - -static INLINE uint32 -load_byte (addr) - SIM_ADDR addr; -{ - uint8 *p = (addr & 0xffffff) + State.mem; - -#ifdef CHECK_ADDR - if ((addr & 0xffffff) > max_mem) - abort (); -#endif - - return p[0]; -} - -static INLINE uint32 -load_half (addr) - SIM_ADDR addr; -{ - uint8 *p = (addr & 0xffffff) + State.mem; - -#ifdef CHECK_ADDR - if ((addr & 0xffffff) > max_mem) - abort (); -#endif - - return p[1] << 8 | p[0]; -} - -static INLINE uint32 -load_3_byte (addr) - SIM_ADDR addr; -{ - uint8 *p = (addr & 0xffffff) + State.mem; - -#ifdef CHECK_ADDR - if ((addr & 0xffffff) > max_mem) - abort (); -#endif - - return p[2] << 16 | p[1] << 8 | p[0]; -} - -static INLINE uint32 -load_word (addr) - SIM_ADDR addr; -{ - uint8 *p = (addr & 0xffffff) + State.mem; - -#ifdef CHECK_ADDR - if ((addr & 0xffffff) > max_mem) - abort (); -#endif - - return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0]; -} - -static INLINE uint32 -load_mem (addr, len) - SIM_ADDR addr; - int len; -{ - uint8 *p = (addr & 0xffffff) + State.mem; - -#ifdef CHECK_ADDR - if ((addr & 0xffffff) > max_mem) - abort (); -#endif - - switch (len) - { - case 1: - return p[0]; - case 2: - return p[1] << 8 | p[0]; - case 3: - return p[2] << 16 | p[1] << 8 | p[0]; - case 4: - return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0]; - default: - abort (); - } -} - -static INLINE void -store_byte (addr, data) - SIM_ADDR addr; - uint32 data; -{ - uint8 *p = (addr & 0xffffff) + State.mem; - -#ifdef CHECK_ADDR - if ((addr & 0xffffff) > max_mem) - abort (); -#endif - - p[0] = data; -} - -static INLINE void -store_half (addr, data) - SIM_ADDR addr; - uint32 data; -{ - uint8 *p = (addr & 0xffffff) + State.mem; - -#ifdef CHECK_ADDR - if ((addr & 0xffffff) > max_mem) - abort (); -#endif - - p[0] = data; - p[1] = data >> 8; -} - -static INLINE void -store_3_byte (addr, data) - SIM_ADDR addr; - uint32 data; -{ - uint8 *p = (addr & 0xffffff) + State.mem; - -#ifdef CHECK_ADDR - if ((addr & 0xffffff) > max_mem) - abort (); -#endif - - p[0] = data; - p[1] = data >> 8; - p[2] = data >> 16; -} - -static INLINE void -store_word (addr, data) - SIM_ADDR addr; - uint32 data; -{ - uint8 *p = (addr & 0xffffff) + State.mem; - -#ifdef CHECK_ADDR - if ((addr & 0xffffff) > max_mem) - abort (); -#endif - - p[0] = data; - p[1] = data >> 8; - p[2] = data >> 16; - p[3] = data >> 24; -} - -/* Function declarations. */ - -uint32 get_word PARAMS ((uint8 *)); -void put_word PARAMS ((uint8 *, uint32)); - -extern uint8 *map PARAMS ((SIM_ADDR addr)); diff --git a/sim/mn10200/simops.c b/sim/mn10200/simops.c deleted file mode 100644 index eccecca..0000000 --- a/sim/mn10200/simops.c +++ /dev/null @@ -1,2449 +0,0 @@ -#include "config.h" - -#include <signal.h> -#ifdef HAVE_UNISTD_H -#include <unistd.h> -#endif -#include "mn10200_sim.h" -#include "simops.h" -#include "targ-vals.h" -#include "bfd.h" -#include <errno.h> -#include <sys/stat.h> -#include <sys/times.h> -#include <sys/time.h> - -#define REG0(X) ((X) & 0x3) -#define REG1(X) (((X) & 0xc) >> 2) -#define REG0_4(X) (((X) & 0x30) >> 4) -#define REG0_8(X) (((X) & 0x300) >> 8) -#define REG1_8(X) (((X) & 0xc00) >> 10) -#define REG0_16(X) (((X) & 0x30000) >> 16) -#define REG1_16(X) (((X) & 0xc0000) >> 18) -#define TRUNC(X) ((X) & 0xffffff) - -/* mov imm8, dn */ -void OP_8000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff); -} - -/* mov dn, dm */ -void OP_80 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)]; -} - -/* mov dm, an */ -void OP_F230 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)]; -} - -/* mov an, dm */ -void OP_F2F0 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)]; -} - -/* mov an, am */ -void OP_F270 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)]; -} - -/* mov psw, dn */ -void OP_F3F0 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] = PSW & 0xffff; -} - -/* mov dn, psw */ -void OP_F3D0 (insn, extension) - unsigned long insn, extension; -{ - PSW = State.regs[REG_D0 + REG1 (insn)] & 0xffff ; -} - -/* mov mdr, dn */ -void OP_F3E0 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR] & 0xffff; -} - -/* mov dn, mdr */ -void OP_F3C0 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)] & 0xffff; -} - -/* mov (an), dm */ -void OP_20 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] - = SEXT16 (load_half (State.regs[REG_A0 + REG1 (insn)])); -} - -/* mov (d8,an), dm */ -void OP_6000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_8 (insn)] - = SEXT16 (load_half ((State.regs[REG_A0 + REG1_8 (insn)] - + SEXT8 (insn & 0xff)))); -} - -/* mov (d16,an), dm */ -void OP_F7C00000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = SEXT16 (load_half ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT16 (insn & 0xffff)))); -} - -/* mov (d24,am), dn */ -void OP_F4800000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = SEXT16 (load_half ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT24 (((insn & 0xffff) << 8) + extension)))); -} - -/* mov (di,an), dm */ -void OP_F140 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] - = SEXT16 (load_half ((State.regs[REG_A0 + REG1 (insn)] - + State.regs[REG_D0 + REG0_4 (insn)]))); -} - -/* mov (abs16), dn */ -void OP_C80000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] = SEXT16 (load_half ((insn & 0xffff))); -} - -/* mov (abs24), dn */ -void OP_F4C00000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = SEXT16 (load_half ((((insn & 0xffff) << 8) + extension))); -} - -/* mov (d8,an), am */ -void OP_7000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0_8 (insn)] - = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_8 (insn)] - + SEXT8 (insn & 0xff)))); -} - -/* mov (d16,an), am */ -void OP_F7B00000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0_16 (insn)] - = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT16 (insn & 0xffff)))); -} - -/* mov (d24,am), an */ -void OP_F4F00000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0_16 (insn)] - = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT24 (((insn & 0xffff) << 8) + extension)))); -} - -/* mov (di,an), am */ -void OP_F100 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0 (insn)] - = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1 (insn)] - + State.regs[REG_D0 + REG0_4 (insn)]))); -} - -/* mov (abs16), an */ -void OP_F7300000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0_16 (insn)] = SEXT24 (load_3_byte ((insn & 0xffff))); -} - -/* mov (abs24), an */ -void OP_F4D00000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0_16 (insn)] - = SEXT24 (load_3_byte ((((insn & 0xffff) << 8) + extension))); -} - -/* mov dm, (an) */ -void OP_0 (insn, extension) - unsigned long insn, extension; -{ - store_half (State.regs[REG_A0 + REG1 (insn)], - State.regs[REG_D0 + REG0 (insn)]); -} - -/* mov dm, (d8,an) */ -void OP_4000 (insn, extension) - unsigned long insn, extension; -{ - store_half (State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff), - State.regs[REG_D0 + REG0_8 (insn)]); -} - -/* mov dm, (d16,an) */ -void OP_F7800000 (insn, extension) - unsigned long insn, extension; -{ - store_half (State.regs[REG_A0 + REG1_16 (insn)] + SEXT16 (insn & 0xffff), - State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* mov dm, (d24,am) */ -void OP_F4000000 (insn, extension) - unsigned long insn, extension; -{ - store_half ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT24 (((insn & 0xffff) << 8) + extension)), - State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* mov dm, (di,an) */ -void OP_F1C0 (insn, extension) - unsigned long insn, extension; -{ - store_half ((State.regs[REG_A0 + REG1 (insn)] - + State.regs[REG_D0 + REG0_4 (insn)]), - State.regs[REG_D0 + REG0 (insn)]); -} - -/* mov dn, (abs16) */ -void OP_C00000 (insn, extension) - unsigned long insn, extension; -{ - store_half ((insn & 0xffff), State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* mov dn, (abs24) */ -void OP_F4400000 (insn, extension) - unsigned long insn, extension; -{ - store_half (SEXT24 (((insn & 0xffff) << 8) + extension), - State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* mov am, (d8,an) */ -void OP_5000 (insn, extension) - unsigned long insn, extension; -{ - store_3_byte (State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff), - State.regs[REG_A0 + REG0_8 (insn)]); -} - -/* mov am, (d16,an) */ -void OP_F7A00000 (insn, extension) - unsigned long insn, extension; -{ - store_3_byte (State.regs[REG_A0 + REG1_16 (insn)] + SEXT16 (insn & 0xffff), - State.regs[REG_A0 + REG0_16 (insn)]); -} - -/* mov am, (d24,an) */ -void OP_F4100000 (insn, extension) - unsigned long insn, extension; -{ - store_3_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT24 (((insn & 0xffff) << 8) + extension)), - State.regs[REG_A0 + REG0_16 (insn)]); -} - -/* mov am, (di,an) */ -void OP_F180 (insn, extension) - unsigned long insn, extension; -{ - store_3_byte ((State.regs[REG_A0 + REG1 (insn)] - + State.regs[REG_D0 + REG0_4 (insn)]), - State.regs[REG_A0 + REG0 (insn)]); -} - -/* mov an, (abs16) */ -void OP_F7200000 (insn, extension) - unsigned long insn, extension; -{ - store_3_byte ((insn & 0xffff), State.regs[REG_A0 + REG0_16 (insn)]); -} - -/* mov an, (abs24) */ -void OP_F4500000 (insn, extension) - unsigned long insn, extension; -{ - store_3_byte (SEXT24 (((insn & 0xffff) << 8) + extension), - State.regs[REG_A0 + REG0_16 (insn)]); -} - -/* mov imm16, dn */ -void OP_F80000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] = SEXT16 (insn & 0xffff); -} - -/* mov imm24, dn */ -void OP_F4700000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = SEXT24 (((insn & 0xffff) << 8) + extension); -} - -/* mov imm16, an */ -void OP_DC0000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0_16 (insn)] = insn & 0xffff; -} - -/* mov imm24, an */ -void OP_F4740000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_A0 + REG0_16 (insn)] - = SEXT24 (((insn & 0xffff) << 8) + extension); -} - -/* movx (d8,an), dm */ -void OP_F57000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_8 (insn)] - = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_8 (insn)] - + SEXT8 (insn & 0xff)))); -} - -/* movx (d16,an), dm */ -void OP_F7700000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT16 (insn & 0xffff)))); -} - -/* movx (d24,am), dn */ -void OP_F4B00000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT24 (((insn & 0xffff) << 8) + extension)))); -} - -/* movx dm, (d8,an) */ -void OP_F55000 (insn, extension) - unsigned long insn, extension; -{ - store_3_byte (State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff), - State.regs[REG_D0 + REG0_8 (insn)]); -} - -/* movx dm, (d16,an) */ -void OP_F7600000 (insn, extension) - unsigned long insn, extension; -{ - store_3_byte (State.regs[REG_A0 + REG1_16 (insn)] + SEXT16 (insn & 0xffff), - State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* movx dm, (d24,am) */ -void OP_F4300000 (insn, extension) - unsigned long insn, extension; -{ - store_3_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT24 (((insn & 0xffff) << 8) + extension)), - State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* movb (d8,an), dm */ -void OP_F52000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_8 (insn)] - = SEXT8 (load_byte ((State.regs[REG_A0 + REG1_8 (insn)] - + SEXT8 (insn & 0xff)))); -} - -/* movb (d16,an), dm */ -void OP_F7D00000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = SEXT8 (load_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT16 (insn & 0xffff)))); -} - -/* movb (d24,am), dn */ -void OP_F4A00000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = SEXT8 (load_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT24 (((insn & 0xffff) << 8) + extension)))); -} - -/* movb (di,an), dm */ -void OP_F040 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] - = SEXT8 (load_byte ((State.regs[REG_A0 + REG1 (insn)] - + State.regs[REG_D0 + REG0_4 (insn)]))); -} - -/* mov (abs24), dn */ -void OP_F4C40000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = SEXT8 (load_byte ((((insn & 0xffff) << 8) + extension))); -} - -/* movb dm, (an) */ -void OP_10 (insn, extension) - unsigned long insn, extension; -{ - store_byte (State.regs[REG_A0 + REG1 (insn)], - State.regs[REG_D0 + REG0 (insn)]); -} - -/* movb dm, (d8,an) */ -void OP_F51000 (insn, extension) - unsigned long insn, extension; -{ - store_byte (State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff), - State.regs[REG_D0 + REG0_8 (insn)]); -} - -/* movb dm, (d16,an) */ -void OP_F7900000 (insn, extension) - unsigned long insn, extension; -{ - store_byte (State.regs[REG_A0 + REG1_16 (insn)] + SEXT16 (insn & 0xffff), - State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* movb dm, (d24,am) */ -void OP_F4200000 (insn, extension) - unsigned long insn, extension; -{ - store_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT24 (((insn & 0xffff) << 8) + extension)), - State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* movb dm, (di,an) */ -void OP_F0C0 (insn, extension) - unsigned long insn, extension; -{ - store_byte ((State.regs[REG_A0 + REG1 (insn)] - + State.regs[REG_D0 + REG0_4 (insn)]), - State.regs[REG_D0 + REG0 (insn)]); -} - -/* movb dn, (abs16) */ -void OP_C40000 (insn, extension) - unsigned long insn, extension; -{ - store_byte ((insn & 0xffff), State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* movb dn, (abs24) */ -void OP_F4440000 (insn, extension) - unsigned long insn, extension; -{ - store_byte (SEXT24 (((insn & 0xffff) << 8) + extension), - State.regs[REG_D0 + REG0_16 (insn)]); -} - -/* movbu (an), dm */ -void OP_30 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] - = load_byte (State.regs[REG_A0 + REG1 (insn)]); -} - -/* movbu (d8,an), dm */ -void OP_F53000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_8 (insn)] - = load_byte ((State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff))); -} - -/* movbu (d16,an), dm */ -void OP_F7500000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = load_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT16 (insn & 0xffff))); -} - -/* movbu (d24,am), dn */ -void OP_F4900000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = load_byte ((State.regs[REG_A0 + REG1_16 (insn)] - + SEXT24 (((insn & 0xffff) << 8) + extension))); -} - -/* movbu (di,an), dm */ -void OP_F080 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] - = load_byte ((State.regs[REG_A0 + REG1 (insn)] - + State.regs[REG_D0 + REG0_4 (insn)])); -} - -/* movbu (abs16), dn */ -void OP_CC0000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff)); -} - -/* movbu (abs24), dn */ -void OP_F4C80000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0_16 (insn)] - = load_byte ((((insn & 0xffff) << 8) + extension)); -} - -/* ext dn */ -void OP_F3C1 (insn, extension) - unsigned long insn, extension; -{ - if (State.regs[REG_D0 + REG1 (insn)] & 0x8000) - State.regs[REG_MDR] = 0xffff; - else - State.regs[REG_MDR] = 0; -} - -/* extx dn */ -void OP_B0 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] = SEXT16 (State.regs[REG_D0 + REG0 (insn)]); -} - -/* extxu dn */ -void OP_B4 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG0 (insn)] & 0xffff; -} - -/* extxb dn */ -void OP_B8 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]); -} - -/* extxbu dn */ -void OP_BC (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG0 (insn)] & 0xff; -} - -/* add dn,dm */ -void OP_90 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]); - value = TRUNC (reg1 + reg2); - State.regs[REG_D0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (reg2 & 0xffff)); - cx = (value < reg1) || (value < reg2); - v = ((reg2 & 0x8000) == (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) == (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* add dm, an */ -void OP_F200 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]); - value = TRUNC (reg1 + reg2); - State.regs[REG_A0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (reg2 & 0xffff)); - cx = (value < reg1) || (value < reg2); - v = ((reg2 & 0x8000) == (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) == (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* add an, dm */ -void OP_F2C0 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]); - value = TRUNC (reg1 + reg2); - State.regs[REG_D0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (reg2 & 0xffff)); - cx = (value < reg1) || (value < reg2); - v = ((reg2 & 0x8000) == (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) == (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* add an,am */ -void OP_F240 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]); - value = TRUNC (reg1 + reg2); - State.regs[REG_A0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (reg2 & 0xffff)); - cx = (value < reg1) || (value < reg2); - v = ((reg2 & 0x8000) == (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) == (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* add imm8, dn */ -void OP_D400 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG0_8 (insn)]); - imm = TRUNC (SEXT8 (insn & 0xff)); - value = TRUNC (reg1 + imm); - State.regs[REG_D0 + REG0_8 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (imm & 0xffff)); - cx = (value < reg1) || (value < imm); - v = ((reg1 & 0x8000) == (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) == (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* add imm16, dn */ -void OP_F7180000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]); - imm = TRUNC (SEXT16 (insn & 0xffff)); - value = TRUNC (reg1 + imm); - State.regs[REG_D0 + REG0_16 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (imm & 0xffff)); - cx = (value < reg1) || (value < imm); - v = ((reg1 & 0x8000) == (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) == (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* add imm24,dn */ -void OP_F4600000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]); - imm = TRUNC (((insn & 0xffff) << 8) + extension); - value = TRUNC (reg1 + imm); - State.regs[REG_D0 + REG0_16 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (imm & 0xffff)); - cx = (value < reg1) || (value < imm); - v = ((reg1 & 0x8000) == (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) == (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* add imm8, an */ -void OP_D000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG0_8 (insn)]); - imm = TRUNC (SEXT8 (insn & 0xff)); - value = TRUNC (reg1 + imm); - State.regs[REG_A0 + REG0_8 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (imm & 0xffff)); - cx = (value < reg1) || (value < imm); - v = ((reg1 & 0x8000) == (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) == (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* add imm16, an */ -void OP_F7080000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]); - imm = TRUNC (SEXT16 (insn & 0xffff)); - value = TRUNC (reg1 + imm); - State.regs[REG_A0 + REG0_16 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (imm & 0xffff)); - cx = (value < reg1) || (value < imm); - v = ((reg1 & 0x8000) == (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) == (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* add imm24, an */ -void OP_F4640000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]); - imm = TRUNC (((insn & 0xffff) << 8) + extension); - value = TRUNC (reg1 + imm); - State.regs[REG_A0 + REG0_16 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) || ((value & 0xffff) < (imm & 0xffff)); - cx = (value < reg1) || (value < imm); - v = ((reg1 & 0x8000) == (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) == (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* addc dm,dn */ -void OP_F280 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]); - value = TRUNC (reg1 + reg2 + ((PSW & PSW_CF) != 0)); - State.regs[REG_D0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((value & 0xffff) < (reg1 & 0xffff)) - || ((value & 0xffff) < (reg2 & 0xffff)); - cx = (value < reg1) || (value < reg2); - v = ((reg2 & 0x8000) == (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) == (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* addnf imm8, an */ -void OP_F50C00 (insn, extension) - unsigned long insn, extension; -{ - unsigned long reg1, imm, value; - - reg1 = State.regs[REG_A0 + REG0_8 (insn)]; - imm = SEXT8 (insn & 0xff); - value = reg1 + imm; - State.regs[REG_A0 + REG0_8 (insn)] = TRUNC (value); -} - -/* sub dn, dm */ -void OP_A0 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]); - value = TRUNC (reg2 - reg1); - State.regs[REG_D0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) > (reg2 & 0xffff)); - cx = (reg1 > reg2); - v = ((reg2 & 0x8000) != (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) != (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* sub dm, an */ -void OP_F210 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]); - value = TRUNC (reg2 - reg1); - State.regs[REG_A0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) > (reg2 & 0xffff)); - cx = (reg1 > reg2); - v = ((reg2 & 0x8000) != (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) != (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* sub an, dm */ -void OP_F2D0 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]); - value = TRUNC (reg2 - reg1); - State.regs[REG_D0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) > (reg2 & 0xffff)); - cx = (reg1 > reg2); - v = ((reg2 & 0x8000) != (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) != (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* sub an, am */ -void OP_F250 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]); - value = TRUNC (reg2 - reg1); - State.regs[REG_A0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) > (reg2 & 0xffff)); - cx = (reg1 > reg2); - v = ((reg2 & 0x8000) != (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) != (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* sub imm16, dn */ -void OP_F71C0000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]); - imm = TRUNC (SEXT16 (insn & 0xffff)); - value = TRUNC (reg1 - imm); - State.regs[REG_D0 + REG0_16 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) < (imm & 0xffff)); - cx = (reg1 < imm); - v = ((reg1 & 0x8000) != (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) != (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* sub imm24, dn */ -void OP_F4680000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]); - imm = TRUNC (((insn & 0xffff) << 8) + extension); - value = TRUNC (reg1 - imm); - State.regs[REG_D0 + REG0_16 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) < (imm & 0xffff)); - cx = (reg1 < imm); - v = ((reg1 & 0x8000) != (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) != (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* sub imm16, an */ -void OP_F70C0000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]); - imm = TRUNC (SEXT16 (insn & 0xffff)); - value = TRUNC (reg1 - imm); - State.regs[REG_A0 + REG0_16 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) < (imm & 0xffff)); - cx = (reg1 < imm); - v = ((reg1 & 0x8000) != (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) != (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* sub imm24, an */ -void OP_F46C0000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]); - imm = TRUNC (((insn & 0xffff) << 8) + extension); - value = TRUNC (reg1 - imm); - State.regs[REG_A0 + REG0_16 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) < (imm & 0xffff)); - cx = (reg1 < imm); - v = ((reg1 & 0x8000) != (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) != (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* subc dm, dn */ -void OP_F290 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]); - value = TRUNC (reg2 - reg1 - ((PSW & PSW_CF) != 0)); - State.regs[REG_D0 + REG0 (insn)] = value; - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) > (reg2 & 0xffff)); - cx = (reg1 > reg2); - v = ((reg2 & 0x8000) != (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) != (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* mul dn, dm */ -void OP_F340 (insn, extension) - unsigned long insn, extension; -{ - unsigned long temp; - int n, z; - - temp = (SEXT16 (State.regs[REG_D0 + REG0 (insn)] & 0xffff) - * SEXT16 ((State.regs[REG_D0 + REG1 (insn)] & 0xffff))); - State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffff; - State.regs[REG_MDR] = temp >> 16; - z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* mulu dn, dm */ -void OP_F350 (insn, extension) - unsigned long insn, extension; -{ - unsigned long temp; - int n, z; - - temp = ((State.regs[REG_D0 + REG0 (insn)] & 0xffff) - * (State.regs[REG_D0 + REG1 (insn)] & 0xffff)); - State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffff; - State.regs[REG_MDR] = temp >> 16; - z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - - -/* divu dm, dn */ -void OP_F360 (insn, extension) - unsigned long insn, extension; -{ - unsigned long temp; - int n, z; - - temp = State.regs[REG_MDR]; - temp &= 0xffff; - temp <<= 16; - temp |= (State.regs[REG_D0 + REG0 (insn)] & 0xffff); - State.regs[REG_MDR] = (temp - % (unsigned long)(State.regs[REG_D0 + REG1 (insn)] & 0xffff)); - temp /= (unsigned long)(State.regs[REG_D0 + REG1 (insn)] & 0xffff); - State.regs[REG_D0 + REG0 (insn)] = temp & 0xffff; - z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* cmp imm8, dn */ -void OP_D800 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG0_8 (insn)]); - imm = TRUNC (SEXT8 (insn & 0xff)); - value = TRUNC (reg1 - imm); - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) < (imm & 0xffff)); - cx = (reg1 < imm); - v = ((reg1 & 0x8000) != (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) != (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); -} - -/* cmp dn, dm */ -void OP_F390 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]); - value = TRUNC (reg2 - reg1); - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) > (reg2 & 0xffff)); - cx = (reg1 > reg2); - v = ((reg2 & 0x8000) != (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) != (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)); -} - -/* cmp dm, an */ -void OP_F220 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]); - value = TRUNC (reg2 - reg1); - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) > (reg2 & 0xffff)); - cx = (reg1 > reg2); - v = ((reg2 & 0x8000) != (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) != (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)); -} - -/* cmp an, dm */ -void OP_F2E0 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]); - value = TRUNC (reg2 - reg1); - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) > (reg2 & 0xffff)); - cx = (reg1 > reg2); - v = ((reg2 & 0x8000) != (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) != (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)); -} - -/* cmp an, am */ -void OP_F260 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, reg2, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]); - reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]); - value = TRUNC (reg2 - reg1); - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) > (reg2 & 0xffff)); - cx = (reg1 > reg2); - v = ((reg2 & 0x8000) != (reg1 & 0x8000) - && (reg2 & 0x8000) != (value & 0x8000)); - vx = ((reg2 & 0x800000) != (reg1 & 0x800000) - && (reg2 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)); -} - -/* cmp imm16, dn */ -void OP_F7480000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]); - imm = TRUNC (SEXT16 (insn & 0xffff)); - value = TRUNC (reg1 - imm); - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) < (imm & 0xffff)); - cx = (reg1 < imm); - v = ((reg1 & 0x8000) != (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) != (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)); -} - -/* cmp imm24, dn */ -void OP_F4780000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]); - imm = TRUNC (((insn & 0xffff) << 8) + extension); - value = TRUNC (reg1 - imm); - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) < (imm & 0xffff)); - cx = (reg1 < imm); - v = ((reg1 & 0x8000) != (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) != (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)); -} - -/* cmp imm16, an */ -void OP_EC0000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]); - imm = TRUNC (insn & 0xffff); - value = TRUNC (reg1 - imm); - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) < (imm & 0xffff)); - cx = (reg1 < imm); - v = ((reg1 & 0x8000) != (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) != (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)); -} - -/* cmp imm24, an */ -void OP_F47C0000 (insn, extension) - unsigned long insn, extension; -{ - int z, c, n, v, zx, cx, nx, vx; - unsigned long reg1, imm, value; - - reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]); - imm = TRUNC (((insn & 0xffff) << 8) + extension); - value = TRUNC (reg1 - imm); - - z = ((value & 0xffff) == 0); - zx = (value == 0); - n = (value & 0x8000); - nx = (value & 0x800000); - c = ((reg1 & 0xffff) < (imm & 0xffff)); - cx = (reg1 < imm); - v = ((reg1 & 0x8000) != (imm & 0x8000) - && (reg1 & 0x8000) != (value & 0x8000)); - vx = ((reg1 & 0x800000) != (imm & 0x800000) - && (reg1 & 0x800000) != (value & 0x800000)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF - | PSW_ZX | PSW_NX | PSW_CX | PSW_VX); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0) - | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0) - | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0)); - - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0) - | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)); -} - -/* and dn, dm */ -void OP_F300 (insn, extension) - unsigned long insn, extension; -{ - int n, z; - unsigned long temp; - - temp = State.regs[REG_D0 + REG0 (insn)] & State.regs[REG_D0 + REG1 (insn)]; - temp &= 0xffff; - State.regs[REG_D0 + REG0 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* and imm8, dn */ -void OP_F50000 (insn, extension) - unsigned long insn, extension; -{ - int n, z; - unsigned long temp; - - temp = State.regs[REG_D0 + REG0_8 (insn)] & (insn & 0xff); - temp &= 0xffff; - State.regs[REG_D0 + REG0_8 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0_8 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0_8 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* and imm16, dn */ -void OP_F7000000 (insn, extension) - unsigned long insn, extension; -{ - int n, z; - unsigned long temp; - - temp = State.regs[REG_D0 + REG0_16 (insn)] & (insn & 0xffff); - temp &= 0xffff; - State.regs[REG_D0 + REG0_16 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0_16 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0_16 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* and imm16, psw */ -void OP_F7100000 (insn, extension) - unsigned long insn, extension; -{ - PSW &= (insn & 0xffff); -} - -/* or dn, dm */ -void OP_F310 (insn, extension) - unsigned long insn, extension; -{ - int n, z; - unsigned long temp; - - temp = State.regs[REG_D0 + REG0 (insn)] | State.regs[REG_D0 + REG1 (insn)]; - temp &= 0xffff; - State.regs[REG_D0 + REG0 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* or imm8, dn */ -void OP_F50800 (insn, extension) - unsigned long insn, extension; -{ - int n, z; - unsigned long temp; - - temp = State.regs[REG_D0 + REG0_8 (insn)] | (insn & 0xff); - temp &= 0xffff; - State.regs[REG_D0 + REG0_8 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0_8 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0_8 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* or imm16, dn */ -void OP_F7400000 (insn, extension) - unsigned long insn, extension; -{ - int n, z; - unsigned long temp; - - temp = State.regs[REG_D0 + REG0_16 (insn)] | (insn & 0xffff); - temp &= 0xffff; - State.regs[REG_D0 + REG0_16 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0_16 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0_16 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* or imm16, psw */ -void OP_F7140000 (insn, extension) - unsigned long insn, extension; -{ - PSW |= (insn & 0xffff); -} - -/* xor dn, dm */ -void OP_F320 (insn, extension) - unsigned long insn, extension; -{ - int n, z; - unsigned long temp; - - temp = State.regs[REG_D0 + REG0 (insn)] ^ State.regs[REG_D0 + REG1 (insn)]; - temp &= 0xffff; - State.regs[REG_D0 + REG0 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* xor imm16, dn */ -void OP_F74C0000 (insn, extension) - unsigned long insn, extension; -{ - int n, z; - unsigned long temp; - - temp = State.regs[REG_D0 + REG0_16 (insn)] ^ (insn & 0xffff); - temp &= 0xffff; - State.regs[REG_D0 + REG0_16 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0_16 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0_16 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* not dn */ -void OP_F3E4 (insn, extension) - unsigned long insn, extension; -{ - int n, z; - unsigned long temp; - - temp = ~State.regs[REG_D0 + REG0 (insn)]; - temp &= 0xffff; - State.regs[REG_D0 + REG0 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)); -} - -/* asr dn */ -void OP_F338 (insn, extension) - unsigned long insn, extension; -{ - long temp; - int z, n, c, high; - - temp = State.regs[REG_D0 + REG0 (insn)] & 0xffff; - c = temp & 1; - high = temp & 0x8000; - temp >>= 1; - temp |= high; - temp &= 0xffff; - State.regs[REG_D0 + REG0 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0)); -} - -/* lsr dn */ -void OP_F33C (insn, extension) - unsigned long insn, extension; -{ - int z, n, c; - long temp; - - temp = State.regs[REG_D0 + REG0 (insn)] & 0xffff; - c = temp & 1; - temp >>= 1; - temp &= 0xffff; - State.regs[REG_D0 + REG0 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0 (insn)] |= temp; - z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0; - n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0)); -} - -/* ror dn */ -void OP_F334 (insn, extension) - unsigned long insn, extension; -{ - unsigned long value; - int c,n,z; - - value = State.regs[REG_D0 + REG0 (insn)] & 0xffff; - c = (value & 0x1); - - value >>= 1; - value |= (PSW & PSW_CF ? 0x8000 : 0); - value &= 0xffff; - State.regs[REG_D0 + REG0 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0 (insn)] |= value; - z = (value == 0); - n = (value & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0)); -} - -/* rol dn */ -void OP_F330 (insn, extension) - unsigned long insn, extension; -{ - unsigned long value; - int c,n,z; - - value = State.regs[REG_D0 + REG0 (insn)] & 0xffff; - c = (value & 0x8000) ? 1 : 0; - - value <<= 1; - value |= (PSW & PSW_CF ? 0x1 : 0); - value &= 0xffff; - State.regs[REG_D0 + REG0 (insn)] &= ~0xffff; - State.regs[REG_D0 + REG0 (insn)] |= value; - z = (value == 0); - n = (value & 0x8000) != 0; - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0)); -} - -/* btst imm8, dn */ -void OP_F50400 (insn, extension) - unsigned long insn, extension; -{ - unsigned long temp; - int z; - - temp = State.regs[REG_D0 + REG0_8 (insn)]; - temp &= (insn & 0xff); - z = (temp == 0); - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= (z ? PSW_ZF : 0); -} - -/* btst imm16, dn */ -void OP_F7040000 (insn, extension) - unsigned long insn, extension; -{ - unsigned long temp; - int z, n, c; - - temp = State.regs[REG_D0 + REG0_16 (insn)]; - c = temp & 0x1; - temp &= (insn & 0xffff); - n = (temp & 0x8000) != 0; - z = (temp == 0); - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= (z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0); -} - -/* bset dm, (an) */ -void OP_F020 (insn, extension) - unsigned long insn, extension; -{ - unsigned long temp; - int z; - - temp = load_byte (State.regs[REG_A0 + REG1 (insn)]); - z = (temp & State.regs[REG_D0 + REG0 (insn)]) == 0; - temp |= State.regs[REG_D0 + REG0 (insn)]; - store_byte (State.regs[REG_A0 + REG1 (insn)], temp); - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= (z ? PSW_ZF : 0); -} - -/* bclr dm, (an) */ -void OP_F030 (insn, extension) - unsigned long insn, extension; -{ - unsigned long temp; - int z; - - temp = load_byte (State.regs[REG_A0 + REG1 (insn)]); - z = (temp & State.regs[REG_D0 + REG0 (insn)]) == 0; - temp = temp & ~State.regs[REG_D0 + REG0 (insn)]; - store_byte (State.regs[REG_A0 + REG1 (insn)], temp); - PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF); - PSW |= (z ? PSW_ZF : 0); -} - -/* beqx label:8 */ -void OP_F5E800 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (PSW & PSW_ZX) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bnex label:8 */ -void OP_F5E900 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (!(PSW & PSW_ZX)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bgtx label:8 */ -void OP_F5E100 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (!((PSW & PSW_ZX) - || (((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0)))) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bgex label:8 */ -void OP_F5E200 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (!(((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0))) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* blex label:8 */ -void OP_F5E300 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if ((PSW & PSW_ZX) - || (((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0))) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bltx label:8 */ -void OP_F5E000 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bhix label:8 */ -void OP_F5E500 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (!(((PSW & PSW_CX) != 0) || (PSW & PSW_ZX) != 0)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bccx label:8 */ -void OP_F5E600 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (!(PSW & PSW_CX)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* blsx label:8 */ -void OP_F5E700 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (((PSW & PSW_CX) != 0) || (PSW & PSW_ZX) != 0) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bcsx label:8 */ -void OP_F5E400 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (PSW & PSW_CX) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bvcx label:8 */ -void OP_F5EC00 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (!(PSW & PSW_VX)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bvsx label:8 */ -void OP_F5ED00 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (PSW & PSW_VX) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bncx label:8 */ -void OP_F5EE00 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (!(PSW & PSW_NX)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bnsx label:8 */ -void OP_F5EF00 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (PSW & PSW_NX) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* beq label:8 */ -void OP_E800 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if (PSW & PSW_ZF) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bne label:8 */ -void OP_E900 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if (!(PSW & PSW_ZF)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bgt label:8 */ -void OP_E100 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if (!((PSW & PSW_ZF) - || (((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0)))) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bge label:8 */ -void OP_E200 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if (!(((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0))) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* ble label:8 */ -void OP_E300 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if ((PSW & PSW_ZF) - || (((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0))) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* blt label:8 */ -void OP_E000 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if (((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bhi label:8 */ -void OP_E500 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if (!(((PSW & PSW_CF) != 0) || (PSW & PSW_ZF) != 0)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bcc label:8 */ -void OP_E600 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if (!(PSW & PSW_CF)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bls label:8 */ -void OP_E700 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if (((PSW & PSW_CF) != 0) || (PSW & PSW_ZF) != 0) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bcs label:8 */ -void OP_E400 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - if (PSW & PSW_CF) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bvc label:8 */ -void OP_F5FC00 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (!(PSW & PSW_VF)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bvs label:8 */ -void OP_F5FD00 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (PSW & PSW_VF) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bnc label:8 */ -void OP_F5FE00 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (!(PSW & PSW_NF)) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bns label:8 */ -void OP_F5FF00 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 3 after we return, so - we subtract two here to make things right. */ - if (PSW & PSW_NF) - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* bra label:8 */ -void OP_EA00 (insn, extension) - unsigned long insn, extension; -{ - /* The dispatching code will add 2 after we return, so - we subtract two here to make things right. */ - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff)); -} - -/* jmp (an) */ -void OP_F000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_PC] = TRUNC (State.regs[REG_A0 + REG1 (insn)] - 2); -} - -/* jmp label:16 */ -void OP_FC0000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT16 (insn & 0xffff)); -} - -/* jmp label:24 */ -void OP_F4E00000 (insn, extension) - unsigned long insn, extension; -{ - State.regs[REG_PC] - = TRUNC (State.regs[REG_PC] + (((insn & 0xffff) << 8) + extension)); -} - -/* jsr (an) */ -void OP_F001 (insn, extension) - unsigned long insn, extension; -{ - unsigned int next_pc, sp; - - sp = State.regs[REG_SP]; - sp -= 4; - State.regs[REG_SP] = sp; - next_pc = State.regs[REG_PC] + 2; - State.mem[sp] = next_pc & 0xff; - State.mem[sp+1] = (next_pc & 0xff00) >> 8; - State.mem[sp+2] = (next_pc & 0xff0000) >> 16; - State.regs[REG_PC] = TRUNC (State.regs[REG_A0 + REG1 (insn)] - 2); -} - -/* jsr label:16 */ -void OP_FD0000 (insn, extension) - unsigned long insn, extension; -{ - unsigned int next_pc, sp; - - sp = State.regs[REG_SP]; - sp -= 4; - State.regs[REG_SP] = sp; - next_pc = State.regs[REG_PC] + 3; - State.mem[sp] = next_pc & 0xff; - State.mem[sp+1] = (next_pc & 0xff00) >> 8; - State.mem[sp+2] = (next_pc & 0xff0000) >> 16; - State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT16 (insn & 0xffff)); -} - -/* jsr label:24 */ -void OP_F4E10000 (insn, extension) - unsigned long insn, extension; -{ - unsigned int next_pc, sp; - - sp = State.regs[REG_SP]; - sp -= 4; - State.regs[REG_SP] = sp; - next_pc = State.regs[REG_PC] + 5; - State.mem[sp] = next_pc & 0xff; - State.mem[sp+1] = (next_pc & 0xff00) >> 8; - State.mem[sp+2] = (next_pc & 0xff0000) >> 16; - State.regs[REG_PC] - = TRUNC (State.regs[REG_PC] + (((insn & 0xffff) << 8) + extension)); -} - -/* rts */ -void OP_FE (insn, extension) - unsigned long insn, extension; -{ - unsigned int sp; - - sp = State.regs[REG_SP]; - State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8) - | (State.mem[sp+2] << 16)); - State.regs[REG_PC] -= 1; - State.regs[REG_SP] += 4; -} - -/* rti */ -void OP_EB (insn, extension) - unsigned long insn, extension; -{ - PSW = load_half (State.regs[REG_A0 + 3]); - State.regs[REG_PC] = load_3_byte (State.regs[REG_A0 + 3] + 2) - 1; - State.regs[REG_A0 + 3] += 6; -} - -/* syscall */ -void OP_F010 (insn, extension) - unsigned long insn, extension; -{ - /* We use this for simulated system calls; we may need to change - it to a reserved instruction if we conflict with uses at - Matsushita. */ - int save_errno = errno; - int offset = 6; - errno = 0; - -/* Registers passed to syscall 0 */ - -/* Function number. */ -#define FUNC (State.regs[0]) - -#define PARM1 (State.regs[1]) - -/* Parameters. */ -#define PARM(x, y) (load_mem (State.regs[REG_SP] + x, y)) - -/* Registers set by syscall 0 */ - -#define RETVAL State.regs[0] /* return value */ -#define RETERR State.regs[1] /* return error code */ - -/* Turn a pointer in a register into a pointer into real memory. */ - -#define MEMPTR(x) (State.mem + (x & 0xffffff)) - - switch (FUNC) - { -#if !defined(__GO32__) && !defined(_WIN32) -#ifdef TARGET_SYS_fork - case TARGET_SYS_fork: - RETVAL = fork (); - break; -#endif -#ifdef TARGET_SYS_execve - case TARGET_SYS_execve: - RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM (4, 4)), - (char **)MEMPTR (PARM (8, 4))); - break; -#endif -#ifdef TARGET_SYS_execv - case TARGET_SYS_execv: - RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM (4, 4)), NULL); - break; -#endif -#endif - - case TARGET_SYS_read: - RETVAL = mn10200_callback->read (mn10200_callback, PARM1, - MEMPTR (PARM (4, 4)), PARM (8, 4)); - break; - case TARGET_SYS_write: - RETVAL = (int)mn10200_callback->write (mn10200_callback, PARM1, - MEMPTR (PARM (4, 4)), - PARM (8, 4)); - break; - case TARGET_SYS_lseek: - RETVAL = mn10200_callback->lseek (mn10200_callback, PARM1, - PARM (4, 4), PARM (8, 2)); - break; - case TARGET_SYS_close: - RETVAL = mn10200_callback->close (mn10200_callback, PARM1); - break; - case TARGET_SYS_open: - RETVAL = mn10200_callback->open (mn10200_callback, MEMPTR (PARM1), - PARM (4, 2)); - break; - case TARGET_SYS_exit: - /* EXIT - caller can look in PARM1 to work out the - reason */ - if (PARM1 == 0xdead) - State.exception = SIGABRT; - else - State.exception = SIGQUIT; - State.exited = 1; - break; - - case TARGET_SYS_stat: /* added at hmsi */ - /* stat system call */ - { - struct stat host_stat; - reg_t buf; - - RETVAL = stat (MEMPTR (PARM1), &host_stat); - - buf = PARM (4, 4); - - /* Just wild-assed guesses. */ - store_half (buf, host_stat.st_dev); - store_half (buf + 2, host_stat.st_ino); - store_word (buf + 4, host_stat.st_mode); - store_half (buf + 8, host_stat.st_nlink); - store_half (buf + 10, host_stat.st_uid); - store_half (buf + 12, host_stat.st_gid); - store_half (buf + 14, host_stat.st_rdev); - store_word (buf + 16, host_stat.st_size); - store_word (buf + 20, host_stat.st_atime); - store_word (buf + 28, host_stat.st_mtime); - store_word (buf + 36, host_stat.st_ctime); - } - break; - -#ifdef TARGET_SYS_chown - case TARGET_SYS_chown: - RETVAL = chown (MEMPTR (PARM1), PARM (4, 2), PARM (6, 2)); - break; -#endif - case TARGET_SYS_chmod: - RETVAL = chmod (MEMPTR (PARM1), PARM (4, 2)); - break; -#ifdef TARGET_SYS_time - case TARGET_SYS_time: - RETVAL = time ((time_t *)MEMPTR (PARM1)); - break; -#endif -#ifdef TARGET_SYS_times - case TARGET_SYS_times: - { - struct tms tms; - RETVAL = times (&tms); - store_word (PARM1, tms.tms_utime); - store_word (PARM1 + 4, tms.tms_stime); - store_word (PARM1 + 8, tms.tms_cutime); - store_word (PARM1 + 12, tms.tms_cstime); - break; - } -#endif -#ifdef TARGET_SYS_gettimeofday - case TARGET_SYS_gettimeofday: - { - struct timeval t; - struct timezone tz; - RETVAL = gettimeofday (&t, &tz); - store_word (PARM1, t.tv_sec); - store_word (PARM1 + 4, t.tv_usec); - store_word (PARM (4, 4), tz.tz_minuteswest); - store_word (PARM (4, 4) + 4, tz.tz_dsttime); - break; - } -#endif -#ifdef TARGET_SYS_utime - case TARGET_SYS_utime: - /* Cast the second argument to void *, to avoid type mismatch - if a prototype is present. */ - RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM (4, 4))); - break; -#endif - default: - abort (); - } - RETERR = errno; - errno = save_errno; -} - -/* nop */ -void OP_F6 (insn, extension) - unsigned long insn, extension; -{ -} - -/* breakpoint */ -void -OP_FF (insn, extension) - unsigned long insn, extension; -{ - State.exception = SIGTRAP; - PC -= 1; -} |