2002-06-04 Chris Demetriou <cgd@broadcom.com>

        * sim-main.h (FGRIDX): Remove, replace all uses with...
        (FGR_BASE): New macro.
        (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
        (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
        (NR_FGR, FGR): Likewise.
        * interp.c: Replace all uses of FGRIDX with FGR_BASE.
        * mips.igen: Likewise.

4 files changed, 40 insertions, 28 deletions

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 95b20ba..771edae 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,5 +1,15 @@
 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 
+	* sim-main.h (FGRIDX): Remove, replace all uses with...
+	(FGR_BASE): New macro.
+	(FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
+	(_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
+	(NR_FGR, FGR): Likewise.
+	* interp.c: Replace all uses of FGRIDX with FGR_BASE.
+	* mips.igen: Likewise.
+
+2002-06-04  Chris Demetriou  <cgd@broadcom.com>
+
 	* cp1.c: Add an FSF Copyright notice to this file.
 
 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 35016e3..8cc6318 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -575,7 +575,7 @@ sim_open (kind, cb, abfd, argv)
       {
 	if (rn < 32)
 	  cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
-	else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
+	else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
 	  cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
 	else if ((rn >= 33) && (rn <= 37))
 	  cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
@@ -849,26 +849,26 @@ sim_store_register (sd,rn,memory,length)
 
 
 
-  if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+  if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
     {
-      cpu->fpr_state[rn - FGRIDX] = fmt_uninterpreted;
+      cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
       if (cpu->register_widths[rn] == 32)
 	{
 	  if (length == 8)
 	    {
-	      cpu->fgr[rn - FGRIDX] = 
+	      cpu->fgr[rn - FGR_BASE] = 
 		(unsigned32) T2H_8 (*(unsigned64*)memory);
 	      return 8;
 	    }
 	  else
 	    {
-	      cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
+	      cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
 	      return 4;
 	    }
 	}
       else
 	{
-	  cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
+	  cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
 	  return 8;
 	}
     }
@@ -921,25 +921,25 @@ sim_fetch_register (sd,rn,memory,length)
 
 
   /* Any floating point register */
-  if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+  if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
     {
       if (cpu->register_widths[rn] == 32)
 	{
 	  if (length == 8)
 	    {
 	      *(unsigned64*)memory =
-		H2T_8 ((unsigned32) (cpu->fgr[rn - FGRIDX]));
+		H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
 	      return 8;
 	    }
 	  else
 	    {
-	      *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
+	      *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
 	      return 4;
 	    }
 	}
       else
 	{
-	  *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
+	  *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
 	  return 8;
 	}
     }
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index b282602..874b685 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -4058,11 +4058,11 @@
   if (X)
     {
       if (SizeFGR() == 64)
-	PENDING_FILL((FS + FGRIDX),GPR[RT]);
+	PENDING_FILL((FS + FGR_BASE),GPR[RT]);
       else if ((FS & 0x1) == 0)
 	{
-	  PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
-	  PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
+	  PENDING_FILL(((FS + 1) + FGR_BASE),VH4_8(GPR[RT]));
+	  PENDING_FILL((FS + FGR_BASE),VL4_8(GPR[RT]));
 	}
     }
   else
@@ -4264,10 +4264,10 @@
 	    sim_io_eprintf (SD,
 			    "Warning:  PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
 			    (long) CIA);
-	  PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
+	  PENDING_FILL ((FS + FGR_BASE), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
 	}
       else
-	PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
+	PENDING_FILL ((FS + FGR_BASE), VL4_8(GPR[RT]));
     }
   else /*MFC1*/
     PENDING_FILL (RT, EXTEND32 (FGR[FS]));
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 8087a3a..0c3d17b 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -254,10 +254,10 @@ memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 /* For backward compatibility */
 #define PENDING_FILL(R,VAL) 						\
 do {									\
-  if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)				\
+  if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR)			\
     {									\
-      PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1);			\
-      PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1);	\
+      PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1);			\
+      PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
     }									\
   else									\
     PENDING_SCHED(GPR[(R)], VAL, 1, -1);				\
@@ -350,7 +350,9 @@ struct _sim_cpu {
 #define LAST_EMBED_REGNUM (89)
 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 
-
+#define FP0_REGNUM 38           /* Floating point register 0 (single float) */
+#define FCRCS_REGNUM 70         /* FP control/status */
+#define FCRIR_REGNUM 71         /* FP implementation/revision */
 #endif
 
 
@@ -366,15 +368,6 @@ struct _sim_cpu {
 #define GPR     (&REGISTERS[0])
 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 
-  /* While space is allocated for the floating point registers in the
-     main registers array, they are stored separatly.  This is because
-     their size may not necessarily match the size of either the
-     general-purpose or system specific registers */
-#define NR_FGR  (32)
-#define FGRIDX  (38)
-  fp_word fgr[NR_FGR];
-#define FGR     ((CPU)->fgr)
-
 #define LO      (REGISTERS[33])
 #define HI      (REGISTERS[34])
 #define PCIDX	37
@@ -427,6 +420,15 @@ struct _sim_cpu {
 #define COP0_GPR	((CPU)->cop0_gpr)
 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 
+  /* While space is allocated for the floating point registers in the
+     main registers array, they are stored separatly.  This is because
+     their size may not necessarily match the size of either the
+     general-purpose or system specific registers.  */
+#define NR_FGR    (32)
+#define FGR_BASE  FP0_REGNUM
+  fp_word fgr[NR_FGR];
+#define FGR       ((CPU)->fgr)
+
   /* Keep the current format state for each register: */
   FP_formats fpr_state[32];
 #define FPR_STATE ((CPU)->fpr_state)