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authorJames Lemke <jlemke@cygnus>1998-06-04 20:50:55 +0000
committerJames Lemke <jlemke@cygnus>1998-06-04 20:50:55 +0000
commit037f29c526b22ac1505c81f901b3741204b83d57 (patch)
tree7383e4e9cbd0a7814bc034c0837b4854072f1332 /sim/mips
parentd6b6757b7ab2fca3efc939eea7d33a3d77c30935 (diff)
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Added support for the VU insn D (debug) & T (trace) bits.
Diffstat (limited to 'sim/mips')
-rw-r--r--sim/mips/interp.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index e0ec3e3..07b7e6b 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -3545,7 +3545,10 @@ decode_coproc (SIM_DESC sd,
unsigned_4 data;
/* enum + int calculation, argh! */
id = VU_REG_MST + 16 * id;
- read_vu_misc_reg(&(vu0_device.regs), id, & data);
+ if (id >= VU_REG_CMSAR0)
+ read_vu_special_reg(&vu0_device, id, & data);
+ else
+ read_vu_misc_reg(&(vu0_device.regs), id, & data);
GPR[rt] = EXTEND32(T2H_4(data));
}
}
@@ -3584,8 +3587,11 @@ decode_coproc (SIM_DESC sd,
{
unsigned_4 data = H2T_4(GPR[rt]);
/* enum + int calculation, argh! */
- id = VU_REG_MST + 16 * id;
- write_vu_misc_reg(&(vu0_device.regs), id, & data);
+ id = VU_REG_VI + 16 * id;
+ if (id >= VU_REG_CMSAR0)
+ write_vu_special_reg(&vu0_device, id, & data);
+ else
+ write_vu_misc_reg(&(vu0_device.regs), id, & data);
}
}
else if(i_10_0 == 0x3bf) /* VWAITQ */