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| author | Andrew Cagney <cagney@redhat.com> | 1998-05-25 05:48:34 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-05-25 05:48:34 +0000 |
| commit | ce823781894cd9a9a61f7a446b40833f40bb01d3 (patch) | |
| tree | 6e419b97ccd9c2a3a54b1f710b49c62eab3034c4 /sim/mips | |
| parent | 21b3bc779ca64a3b1d39886a74f0304c8dc96368 (diff) | |
| download | gdb-ce823781894cd9a9a61f7a446b40833f40bb01d3.zip gdb-ce823781894cd9a9a61f7a446b40833f40bb01d3.tar.gz gdb-ce823781894cd9a9a61f7a446b40833f40bb01d3.tar.bz2 | |
Fix mips SWL on 64bit ISA when 32 bit word appears in second half of
64 bit bus.
Test.
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 5a6a0e0..8c192d2 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,10 @@ +Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * mips.igen (do_store_left, do_load_left): Compute nr of left and + right bits and then re-align left hand bytes to correct byte + lanes. Fix incorrect computation in do_store_left when loading + bytes from second word. + start-sanitize-tx3904 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com> |