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| author | Jason Molenda <jmolenda@apple.com> | 2000-02-05 07:30:26 +0000 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 2000-02-05 07:30:26 +0000 |
| commit | dfcd3bfb6f8a213007c20e60060b4e9ec9205205 (patch) | |
| tree | c43f1f196f08266345d283414914033ecc50bd5e /sim/mips | |
| parent | 32edc927faea39b1f7be4654f6ffa03f3e6b16ce (diff) | |
| download | gdb-dfcd3bfb6f8a213007c20e60060b4e9ec9205205.zip gdb-dfcd3bfb6f8a213007c20e60060b4e9ec9205205.tar.gz gdb-dfcd3bfb6f8a213007c20e60060b4e9ec9205205.tar.bz2 | |
import gdb-2000-02-04 snapshot
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/mips/sim-main.c | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 8c3860b..4c72a33 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,8 @@ +Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com> + + * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary + cache don't get ReservedInstruction traps. + 1999-11-29 Mark Salter <msalter@cygnus.com> * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c index 58e63dc..48a37ae 100644 --- a/sim/mips/sim-main.c +++ b/sim/mips/sim-main.c @@ -463,6 +463,7 @@ cache_op (SIM_DESC SD, break; case 1: /* data cache */ + case 3: /* secondary data cache */ switch (op >> 2) { case 0: /* Index Writeback Invalidate */ case 1: /* Index Load Tag */ |