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authorMark Alexander <marka@cygnus>1996-12-28 06:51:58 +0000
committerMark Alexander <marka@cygnus>1996-12-28 06:51:58 +0000
commit39bf0ef4e6797058928dc5c8fe44fb3a26d4f5c4 (patch)
tree780fdc8e4c72d5e3952c04d58c7217dd9b756e7f /sim/mips
parent962873d57435cafc211c6e8b3bd704289fbc24de (diff)
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* gencode.c (build_instruction): Work around MSVC++ code gen bug
that messes up arithmetic shifts.
Diffstat (limited to 'sim/mips')
-rw-r--r--sim/mips/ChangeLog5
-rw-r--r--sim/mips/gencode.c7
2 files changed, 11 insertions, 1 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index c4f7709..fc6c3cf 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
+
+ * gencode.c (build_instruction): Work around MSVC++ code gen bug
+ that messes up arithmetic shifts.
+
Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
* support.h: Use _WIN32 instead of __WIN32__. Also add defs for
diff --git a/sim/mips/gencode.c b/sim/mips/gencode.c
index 023c99d..4f7a327 100644
--- a/sim/mips/gencode.c
+++ b/sim/mips/gencode.c
@@ -1680,6 +1680,11 @@ build_instruction (doisa, features, mips16, insn)
exit(9);
}
+ /* Work around an MSC code generation bug by precomputing a value
+ * with the sign bit set. */
+ if (insn->flags & ARITHMETIC)
+ printf(" %s highbit = (%s)1 << %d;\n", ltype, ltype, bits - 1);
+
/* If register specified shift, then extract the relevant shift amount: */
if (insn->flags & REG)
printf(" op1 &= 0x%02X;\n",(bits - 1));
@@ -1701,7 +1706,7 @@ build_instruction (doisa, features, mips16, insn)
since that would cause an undefined shift of the number of
bits in the type. */
if (insn->flags & ARITHMETIC)
- printf(" GPR[destreg] |= (op1 != 0 && (op2 & ((%s)1 << %d)) ? ((((%s)1 << op1) - 1) << (%d - op1)) : 0);\n",ltype,(bits - 1),ltype,bits);
+ printf(" GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((%s)1 << op1) - 1) << (%d - op1)) : 0);\n",ltype,bits);
/* Ensure WORD values are sign-extended into 64bit registers */
if ((bits == 32) && (gprlen == 64))