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| author | Gavin Romig-Koch <gavin@redhat.com> | 1998-03-09 20:22:45 +0000 |
|---|---|---|
| committer | Gavin Romig-Koch <gavin@redhat.com> | 1998-03-09 20:22:45 +0000 |
| commit | d843d7ca34a11802c15bf99912c1989d52a2e3d1 (patch) | |
| tree | e0b5bb104da1097d38ff13571d30ca096c16ab2c /sim/mips | |
| parent | c391655e30a994ec207e8e352b21a078a9c316bd (diff) | |
| download | gdb-d843d7ca34a11802c15bf99912c1989d52a2e3d1.zip gdb-d843d7ca34a11802c15bf99912c1989d52a2e3d1.tar.gz gdb-d843d7ca34a11802c15bf99912c1989d52a2e3d1.tar.bz2 | |
* mips/vr4320.igen: Mark the insn in here as vr4320 only.
Reorder the insns.
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/vr4320.igen | 54 |
1 files changed, 31 insertions, 23 deletions
diff --git a/sim/mips/vr4320.igen b/sim/mips/vr4320.igen index d040363..7dd3776 100644 --- a/sim/mips/vr4320.igen +++ b/sim/mips/vr4320.igen @@ -47,10 +47,30 @@ +// Multiply, Accumulate +000000,5.RS,5.RT,00000,00000,101000::::MAC +"mac r<RS>, r<RT>" +*vr4320: +{ + SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); +} + +// D-Multiply, Accumulate +000000,5.RS,5.RT,00000,00000,101001::::DMAC +"dmac r<RS>, r<RT>" +*vr4320: +{ + LO = 99 + SignedMultiply (SD_, GPR[RS], GPR[RT]); +} + + + + + // Multiply and Move LO. 000000,5.RS,5.RT,5.RD,00100,101000::::MUL "mul r<RD>, r<RS>, r<RT>" -*mipsI,mipsII,mipsIII,mipsIV: +*vr4320: { SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT])); GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); @@ -59,7 +79,7 @@ // Unsigned Multiply and Move LO. 000000,5.RS,5.RT,5.RD,00101,101000::::MULU "mulu r<RD>, r<RS>, r<RT>" -*mipsI,mipsII,mipsIII,mipsIV: +*vr4320: { SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); @@ -68,42 +88,30 @@ // Multiply and Move HI. 000000,5.RS,5.RT,5.RD,01100,101000::::MULHI "mulhi r<RD>, r<RS>, r<RT>" -*mipsI,mipsII,mipsIII,mipsIV: +*vr4320: { - SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT])); + SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT])); GPR[RD] = High32Bits (SD_, MulAcc (SD_)); } // Unsigned Multiply and Move HI. 000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU "mulhiu r<RD>, r<RS>, r<RT>" -*mipsI,mipsII,mipsIII,mipsIV: +*vr4320: { SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); GPR[RD] = High32Bits (SD_, MulAcc (SD_)); } -// Multiply, Accumulate -000000,5.RS,5.RT,00000,00000,101000::::MAC -"mac r<RS>, r<RT>" -*vr4320: -{ - SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); -} -// D-Multiply, Accumulate -000000,5.RS,5.RT,00000,00000,101001::::DMAC -"dmac r<RS>, r<RT>" -*mipsI,mipsII,mipsIII,mipsIV: -{ - LO = MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]); -} + + // Multiply, Accumulate and Move LO. 000000,5.RS,5.RT,5.RD,00010,101000::::MACC "macc r<RD>, r<RS>, r<RT>" -*mipsI,mipsII,mipsIII,mipsIV: +*vr4320: { SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); @@ -112,7 +120,7 @@ // Unsigned Multiply, Accumulate and Move LO. 000000,5.RS,5.RT,5.RD,00011,101000::::MACCU "maccu r<RD>, r<RS>, r<RT>" -*mipsI,mipsII,mipsIII,mipsIV: +*vr4320: { SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); @@ -121,7 +129,7 @@ // Multiply, Accumulate and Move HI. 000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI "macchi r<RD>, r<RS>, r<RT>" -*mipsI,mipsII,mipsIII,mipsIV: +*vr4320: { SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); GPR[RD] = High32Bits (SD_, MulAcc (SD_)); @@ -130,7 +138,7 @@ // Unsigned Multiply, Accumulate and Move HI. 000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU "macchiu r<RD>, r<RS>, r<RT>" -*mipsI,mipsII,mipsIII,mipsIV: +*vr4320: { SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); GPR[RD] = High32Bits (SD_, MulAcc (SD_)); |