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authorAndrew Cagney <cagney@redhat.com>1998-04-14 14:34:48 +0000
committerAndrew Cagney <cagney@redhat.com>1998-04-14 14:34:48 +0000
commitc0a4c3ba170e91bf93d16e0a6340980f6d62901a (patch)
tree2632698074a0ae78b8d5c070716ffee0a7ba83eb /sim/mips
parent7bf341f4a82e7e038d6d3861a7ce559d2bb8713f (diff)
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Implement 32 bit MIPS16 instructions listed in m16.igen.
Diffstat (limited to 'sim/mips')
-rw-r--r--sim/mips/ChangeLog24
-rw-r--r--sim/mips/Makefile.in2
-rw-r--r--sim/mips/m16.igen3118
-rw-r--r--sim/mips/m16run.c73
-rw-r--r--sim/mips/mips.igen409
-rw-r--r--sim/mips/sim-main.h12
6 files changed, 1078 insertions, 2560 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 499e2b4..fcc40e7 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,5 +1,23 @@
+Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
+ instruction.
+
+ * m16.igen: Implement MIPS16 instructions.
+
+ * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
+ do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
+ do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
+ do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
+ do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
+ bodies of corresponding code from 32 bit insn to these. Also used
+ by MIPS16 versions of functions.
+
+ * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
+ (IMEM16): Drop NR argument from macro.
+
start-sanitize-sky
- Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
+Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (decode_coproc): Add proper 1000000 bit-string at top
of VU lower instruction.
@@ -15,7 +33,7 @@ Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
end-sanitize-sky
start-sanitize-sky
- Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
+Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
* Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
@@ -25,7 +43,7 @@ start-sanitize-sky
end-sanitize-sky
start-sanitize-sky
- Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
+Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (decode_coproc): Do not apply superfluous E (end) flag
to upper code of generated VU instruction.
diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in
index 28ae81c..4f3bb2f 100644
--- a/sim/mips/Makefile.in
+++ b/sim/mips/Makefile.in
@@ -120,7 +120,7 @@ getopt1.o: $(srcdir)/../../libiberty/getopt1.c
../igen/igen:
cd ../igen && $(MAKE)
-IGEN_TRACE= -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
+IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
IGEN_INSN=$(srcdir)/mips.igen
IGEN_DC=$(srcdir)/mips.dc
M16_DC=$(srcdir)/m16.dc
diff --git a/sim/mips/m16.igen b/sim/mips/m16.igen
index b809603..d69fd31 100644
--- a/sim/mips/m16.igen
+++ b/sim/mips/m16.igen
@@ -1,3 +1,5 @@
+// -*- C -*-
+//
//
// MIPS Architecture:
//
@@ -8,2661 +10,899 @@
// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
-// FIXME: Instead of having the code for mips16 instructions here.
-// these instructions should instead call the corresponding 32bit
-// instruction (or a function implementing that instructions code).
+// The MIPS16 codes registers in a special way, map from one to the other.
+// :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
+:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
+:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
+:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
+:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
+
+
+// FIXME:
+//
+// Only the `LB' instruction is implemented. It should be used as a guideline
+// when implementing other instructions.
+//
+// How to handle delayslots (for jumps) and extended lwpc instructions
+// has not been resolved.
+
+
+011101,26.INSTR_INDEX:NORMAL:32::JALX
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+/// {
+/// }
// Load and Store Instructions
-10000,xxx,ddd,55555:RRI:16::LB
+10000,3.RX,3.RY,5.IMMED:RRI:16::LB
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
- }
- }
- }
+ GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
}
-10100,xxx,ddd,55555:RRI:16::LBU
+10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
- }
- }
- }
+ GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
}
-10001,xxx,ddd,HHHHH:RRI:16::LH
+10001,3.RX,3.RY,5.IMMED:RRI:16::LH
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 1;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
- }
- }
- }
-}
-
-
-10101,xxx,ddd,HHHHH:RRI:16::LHU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 1;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
- }
- }
- }
-}
-
-
-10011,xxx,ddd,WWWWW:RRI:16::LW
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
- }
- }
- }
-}
-
-
-10110,ddd,VVVVVVVV,P:RI:16::LWPC
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
- }
- }
- }
-}
-
-
-10010,ddd,VVVVVVVV,s:RI:16::LWSP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
- }
- }
- }
-}
-
-
-10111,xxx,ddd,WWWWW:RRI:16::LWU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
-}
-
-
-00111,xxx,ddd,DDDDD:RRI:16::LD
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 4;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
- }
- }
- }
-}
-
-
-11111100,ddd,5.RD,P:RI64:16::LDPC
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 4;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
- }
- }
- }
-}
-
-
-11111000,ddd,5.RD,s:RI64:16::LDSP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- signed_word op1 = 29;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 4;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
- }
- }
- }
-}
-
-
-11000,xxx,yyy,55555:RRI:16::SB
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
}
-11001,xxx,yyy,HHHHH:RRI:16::SH
+10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 1;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-11011,xxx,yyy,WWWWW:RRI:16::SW
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-11010,yyy,VVVVVVVV,s:RI:16::SWSP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op2 = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-01100010,VVVVVVVV,Q,s:I8:16::SWRASP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0xff;
- signed_word op2 = 31;
- signed_word op1 = 29;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- op2 = GPR[op2];
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-01111,xxx,yyy,DDDDD:RRI:16::SD
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = op2;
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-11111001,yyy,5.RD,s:RI64:16::SDSP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- signed_word op1 = 29;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = op2;
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-11111010,CCCCCCCC,s,Q:I64:16::SDRASP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- signed_word op2 = 31;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- op1 = GPR[op1];
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = op2;
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
+}
+
+
+10011,3.RX,3.RY,5.IMMED:RRI:16::LW
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
+}
+
+
+10110,3.RX,8.IMMED:RI:16::LWPC
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
+ basepc (SD_) & ~3, IMMED << 2));
+}
+
+
+10010,3.RX,8.IMMED:RI:16::LWSP
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
+}
+
+
+10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
+}
+
+
+00111,3.RX,3.RY,5.IMMED:RRI:16,64::LD
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
+}
+
+
+11111,100,3.RY,5.IMMED:RI64:16::LDPC
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
+ basepc (SD_) & ~7, IMMED << 3);
+}
+
+
+11111,000,3.RY,5.IMMED:RI64:16::LDSP
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
+}
+
+
+11000,3.RX,3.RY,5.IMMED:RRI:16::SB
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
+}
+
+
+11001,3.RX,3.RY,5.IMMED:RRI:16::SH
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
+}
+
+
+11011,3.RX,3.RY,5.IMMED:RRI:16::SW
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
+}
+
+
+11010,3.RX,8.IMMED:RI:16::SWSP
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
+}
+
+
+01100,010,8.IMMED:I8:16::SWRASP
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
+}
+
+
+01111,3.RX,3.RY,5.IMMED:RRI:16::SD
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
+}
+
+
+11111,001,3.RY,5.IMMED:RI64:16::SDSP
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
+}
+
+
+11111,010,8.IMMED:I64:16::SDRASP
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
}
// ALU Immediate Instructions
-01101,ddd,UUUUUUUU,Z:RI:16::LI
+01101,3.RX,8.IMMED::RI:16::LI
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = 0;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = (op1 | op2);
- }
+ do_ori (SD_, 0, TRX, IMMED);
}
-01000,xxx,ddd,04444:RRI_A:16::ADDIU
+01000,3.RX,3.RY,0,4.IMMED:RRI_A:16::ADDIU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int op2 = (instruction >> 0) & 0xf;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
- if (op2 >= 0x4000)
- op2 -= 0x8000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x8)
- op2 -= 0x10;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
+ do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}
-01001,www,kkkkkkkk:RI:16::ADDIU8
+01001,3.RX,8.IMMED:RI:16::ADDIU8
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg;
- int op2 = (instruction >> 0) & 0xff;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x80)
- op2 -= 0x100;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
+ do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
}
-01100011,KKKKKKKK,S:I8:16::ADJSP
+01100,011,8.IMMED:I8:16::ADJSP
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- int destreg;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x80)
- op2 -= 0x100;
- op2 <<= 3;
- }
- destreg = op1;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
+ do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}
-00001,ddd,AAAAAAAA,P:RI:16::ADDIUPC
+00001,3.RX,8.IMMED:RI:16::ADDIUPC
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- op2 <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
+ unsigned32 temp = (basepc (SD_) & ~3) + (EXTEND8 (IMMED) << 2);
+ GPR[TRX] = EXTEND32 (temp);
}
-00000,ddd,AAAAAAAA,s:RI:16::ADDIUSP
+00000,3.RX,8.IMMED:RI:16::ADDIUSP
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- op2 <<= 2;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
-}
-
-
-01000,xxx,ddd,14444:RRI_A:16::DADDIU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int op2 = (instruction >> 0) & 0xf;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
- if (op2 >= 0x4000)
- op2 -= 0x8000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x8)
- op2 -= 0x10;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ do_addiu (SD_, SPIDX, TRX, EXTEND8 (IMMED) << 2);
}
-11111101,www,jjjjj:RI64:16::DADDIU5
+01000,3.RX,3.RY,1,4.IMMED:RRI_A:16,64::DADDIU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 5) & 0x7;
- int destreg;
- int op2 = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x10)
- op2 -= 0x20;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}
-11111011,KKKKKKKK,S:I64:16::DADJSP
+11111,101,3.RY,5.IMMED:RI64:16,64::DADDIU5
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- int destreg;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x80)
- op2 -= 0x100;
- op2 <<= 3;
- }
- destreg = op1;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
}
-11111110,ddd,EEEEE,P:RI64:16::DADDIUPC
+11111,011,8.IMMED:I64:16,64::DADJSP
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- int op2 = (instruction >> 0) & 0x1f;
- signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- op2 <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}
-11111111,ddd,EEEEE,s:RI64:16::DADDIUSP
+11111,110,3.RY,5.IMMED:RI64:16,64::DADDIUPC
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- int op2 = (instruction >> 0) & 0x1f;
- signed_word op1 = 29;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- op2 <<= 2;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ GPR[TRY] = (basepc (SD_) & ~3) + (EXTEND5 (IMMED) << 2);
}
-01010,xxx,88888888,T:RI:16::SLTI
+11111,111,3.RY,5.IMMED:RI64:16,64::DADDIUSP
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if ((word64)op1 < (word64)op2)
- GPR[destreg] = 1;
- else
- GPR[destreg] = 0;
- }
+ do_daddiu (SD_, SPIDX, TRY, EXTEND5 (IMMED) << 2);
}
-01011,xxx,88888888,T:RI:16::SLTIU
+01010,3.RX,8.IMMED:RI:16::SLTI
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if ((unsigned64)op1 < (unsigned64)op2)
- GPR[destreg] = 1;
- else
- GPR[destreg] = 0;
- }
+ do_slti (SD_, TRX, T8IDX, IMMED);
}
-11101,xxx,yyy,01010,T:RR:16::CMP
+01011,3.RX,8.IMMED:RI:16::SLTIU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (op1 ^ op2);
- }
+ do_sltiu (SD_, TRX, T8IDX, IMMED);
}
-01110,xxx,UUUUUUUU,T:RI:16::CMPI
+11101,3.RX,3.RY,01010:RR:16::CMP
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (op1 ^ op2);
- }
+ do_xor (SD_, TRX, TRY, T8IDX);
+}
+
+
+01110,3.RX,8.IMMED:RI:16::CMPI
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_xori (SD_, TRX, T8IDX, IMMED);
}
// Two/Three Operand, Register-Type
-11100,xxx,yyy,ddd,01:RRR:16::ADDU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = (instruction >> 2) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
-}
-
-
-11100,xxx,yyy,ddd,11:RRR:16::SUBU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = (instruction >> 2) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 - op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
-}
-
-
-11100,xxx,yyy,ddd,00:RRR:16::DADDU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = (instruction >> 2) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
-}
-
-
-11100,xxx,yyy,ddd,10:RRR:16::DSUBU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = (instruction >> 2) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 - op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
-}
-
-
-11101,xxx,yyy,00010,T:RR:16::SLT
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if ((word64)op1 < (word64)op2)
- GPR[destreg] = 1;
- else
- GPR[destreg] = 0;
- }
-}
-
-
-11101,xxx,yyy,00011,T:RR:16::SLTU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if ((unsigned64)op1 < (unsigned64)op2)
- GPR[destreg] = 1;
- else
- GPR[destreg] = 0;
- }
-}
-
-
-11101,ddd,yyy,01011,Z:RR:16::NEG
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- signed_word op1 = 0;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 - op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
-}
-
-
-11101,www,yyy,01100:RR:16::AND
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (op1 & op2);
- }
-}
-
-
-11101,www,yyy,01101:RR:16::OR
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = (op1 | op2);
- }
-}
-
-
-11101,www,yyy,01110:RR:16::XOR
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (op1 ^ op2);
- }
-}
-
-
-11101,ddd,yyy,01111,Z:RR:16::NOT
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- signed_word op1 = 0;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = ~(op1 | op2);
- }
-}
-
-
-01100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- signed_word op1 = (instruction >> 0) & 0x1f;
- signed_word op2 = 0;
- if (destreg < 2)
- destreg += 16;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = (op1 | op2);
- }
-}
-
-
-01100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 3) & 0x1f;
- signed_word op1 = (instruction >> 0) & 0x7;
- signed_word op2 = 0;
- destreg = (destreg >> 2) | ((destreg & 3) << 3);
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = (op1 | op2);
- }
-}
-
-
-00110,ddd,yyy,sss,00:ISHIFT:16::SLL
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int op1 = (instruction >> 2) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- op1 = (extendval >> 6) & 0x1f;
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = ((unsigned64)op2 << op1);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
+11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_addu (SD_, TRX, TRY, TRZ);
}
-00110,ddd,yyy,sss,10:ISHIFT:16::SRL
+11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int op1 = (instruction >> 2) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- op1 = (extendval >> 6) & 0x1f;
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
+ do_subu (SD_, TRX, TRY, TRZ);
}
-00110,ddd,yyy,sss,11:ISHIFT:16::SRA
+11100,3.RX,3.RY,3.RZ,00:RRR:16,64::DADDU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int op1 = (instruction >> 2) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- op1 = (extendval >> 6) & 0x1f;
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int highbit = (unsigned int)1 << 31;
- GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
- GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
-}
-
-
-11101,xxx,vvv,00100:RR:16::SLLV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- op1 &= 0x1F;
- GPR[destreg] = ((unsigned64)op2 << op1);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
-}
-
-
-11101,xxx,vvv,00110:RR:16::SRLV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- op1 &= 0x1F;
- GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
-}
-
-
-11101,xxx,vvv,00111:RR:16::SRAV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int highbit = (unsigned int)1 << 31;
- op1 &= 0x1F;
- GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
- GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
-}
-
-
-00110,ddd,yyy,[[[,01:ISHIFT:16::DSLL
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int op1 = (instruction >> 2) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = ((unsigned64)op2 << op1);
- }
+ do_daddu (SD_, TRX, TRY, TRZ);
+}
+
+
+11100,3.RX,3.RY,3.RZ,10:RRR:16,64::DSUBU
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_dsubu (SD_, TRX, TRY, TRZ);
+}
+
+
+11101,3.RX,3.RY,00010:RR:16::SLT
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_slt (SD_, TRX, TRY, T8IDX);
+}
+
+
+11101,3.RX,3.RY,00011:RR:16::SLTU
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_sltu (SD_, TRX, TRY, T8IDX);
+}
+
+
+11101,3.RX,3.RY,01011:RR:16::NEG
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_subu (SD_, 0, TRY, TRX);
+}
+
+
+11101,3.RX,3.RY,01100:RR:16::AND
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_and (SD_, TRX, TRY, TRX);
+}
+
+
+11101,3.RX,3.RY,01101:RR:16::OR
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_or (SD_, TRX, TRY, TRX);
+}
+
+
+11101,3.RX,3.RY,01110:RR:16::XOR
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_xor (SD_, TRX, TRY, TRX);
+}
+
+
+11101,3.RX,3.RY,01111:RR:16::NOT
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_nor (SD_, 0, TRY, TRX);
+}
+
+
+01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_or (SD_, R32, 0, TRY);
+}
+
+
+01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_or (SD_, TRZ, 0, (R32H << 3) | R32L);
+}
+
+
+00110,3.RX,3.RY,3.SHAMT,00:ISHIFT:16::SLL
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_sll (SD_, TRY, TRX, SHIFT);
+}
+
+
+00110,3.RX,3.RY,3.SHAMT,10:ISHIFT:16::SRL
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_srl (SD_, TRY, TRX, SHIFT);
+}
+
+
+00110,3.RX,3.RY,3.SHAMT,11:ISHIFT:16::SRA
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_sra (SD_, TRY, TRX, SHIFT);
+}
+
+
+11101,3.RX,3.RY,00100:RR:16::SLLV
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_sllv (SD_, TRX, TRY, TRY);
+}
+
+
+11101,3.RX,3.RY,00110:RR:16::SRLV
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_srlv (SD_, TRX, TRY, TRY);
+}
+
+
+11101,3.RX,3.RY,00111:RR:16::SRAV
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_srav (SD_, TRX, TRY, TRY);
+}
+
+
+00110,3.RX,3.RY,3.SHAMT,01:ISHIFT:16,64::DSLL
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_dsll (SD_, 0, TRY, TRX, SHIFT);
}
-11101,XXX,vvv,01000:RR:16::DSRL
+11101,3.SHAMT,3.RY,01000:RR:16,64::DSRL
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (have_extendval)
- {
- op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = ((unsigned64)(op2) >> op1);
- }
+ do_dsrl (SD_, 0, TRY, TRY, SHIFT);
}
-11101,xxx,vvv,10011:RR:16::DSRA
+11101,3.SHAMT,3.RY,10011:RR:16,64::DSRA
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (have_extendval)
- {
- op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 highbit = (unsigned64)1 << 63;
- GPR[destreg] = ((unsigned64)(op2) >> op1);
- GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
- }
-}
-
-
-11101,xxx,vvv,10100:RR:16::DSLLV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- op1 &= 0x3F;
- GPR[destreg] = ((unsigned64)op2 << op1);
- }
-}
-
-
-11101,xxx,vvv,10110:RR:16::DSRLV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- op1 &= 0x3F;
- GPR[destreg] = ((unsigned64)(op2) >> op1);
- }
-}
-
-
-11101,xxx,vvv,10111:RR:16::DSRAV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 highbit = (unsigned64)1 << 63;
- op1 &= 0x3F;
- GPR[destreg] = ((unsigned64)(op2) >> op1);
- GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
- }
+ do_dsra (SD_, 0, TRY, TRY, SHIFT);
+}
+
+
+11101,3.RX,3.RY,10100:RR:16,64::DSLLV
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_dsllv (SD_, TRX, TRY, TRY);
+}
+
+
+11101,3.RX,3.RY,10110:RR:16,64::DSRLV
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_dsrlv (SD_, TRX, TRY, TRY);
+}
+
+
+11101,3.RX,3.RY,10111:RR:16,64::DSRAV
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_dsrav (SD_, TRX, TRY, TRY);
}
// Multiply /Divide Instructions
-11101,xxx,yyy,11000:RR:16::MULT
+11101,3.RX,3.RY,11000:RR:16::MULT
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Multiplication");
- {
- unsigned64 temp = ((word64) op1 * (word64) op2);
- LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
- HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
- }
- }
+ do_mult (SD_, TRX, TRY, 0);
}
-11101,xxx,yyy,11001:RR:16::MULTU
+11101,3.RX,3.RY,11001:RR:16::MULTU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Multiplication");
- {
- unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
- LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
- HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
- }
- }
+ do_multu (SD_, TRX, TRY, 0);
}
-11101,xxx,yyy,11010:RR:16::DIV
+11101,3.RX,3.RY,11010:RR:16::DIV
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Division");
- {
- int d1 = op1;
- int d2 = op2;
- if (d2 == 0)
- {
- LO = SIGNEXTEND(0x80000000,32);
- HI = SIGNEXTEND(0,32);
- }
- else if (d2 == -1 && d1 == 0x80000000)
- {
- LO = SIGNEXTEND(0x80000000,32);
- HI = SIGNEXTEND(0,32);
- }
- else
- {
- LO = SIGNEXTEND((d1 / d2),32);
- HI = SIGNEXTEND((d1 % d2),32);
- }
- }
- }
+ do_div (SD_, TRX, TRY);
}
-11101,xxx,yyy,11011:RR:16::DIVU
+11101,3.RX,3.RY,11011:RR:16::DIVU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Division");
- {
- unsigned int d1 = op1;
- unsigned int d2 = op2;
- if (d2 == 0)
- {
- LO = SIGNEXTEND(0x80000000,32);
- HI = SIGNEXTEND(0,32);
- }
- else if (d2 == -1 && d1 == 0x80000000)
- {
- LO = SIGNEXTEND(0x80000000,32);
- HI = SIGNEXTEND(0,32);
- }
- else
- {
- LO = SIGNEXTEND((d1 / d2),32);
- HI = SIGNEXTEND((d1 % d2),32);
- }
- }
- }
+ do_divu (SD_, TRX, TRY);
}
-11101,ddd,00010000:RR:16::MFHI
+11101,3.RX,000,10000:RR:16::MFHI
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = HI;
- HIACCESS = 3; /* 3rd instruction will be safe */
- }
+ do_mfhi (SD_, TRX);
}
-11101,ddd,00010010:RR:16::MFLO
+11101,3.RX,000,10010:RR:16::MFLO
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = LO;
- LOACCESS = 3; /* 3rd instruction will be safe */
- }
+ do_mflo (SD_, TRX);
}
-11101,xxx,yyy,11100:RR:16::DMULT
+11101,3.RX,3.RY,11100:RR:16,64::DMULT
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Multiplication");
- {
- unsigned64 mid;
- unsigned64 midhi;
- unsigned64 temp;
- int sign = 0;
- if (op1 < 0) { op1 = - op1; ++sign; }
- if (op2 < 0) { op2 = - op2; ++sign; }
- LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
- HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
- mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
- midhi = SET64HI(VL4_8(mid));
- temp = (LO + midhi);
- if ((temp == midhi) ? (LO != 0) : (temp < midhi))
- HI += 1;
- HI += VH4_8(mid);
- mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
- midhi = SET64HI(VL4_8(mid));
- LO = (temp + midhi);
- if ((LO == midhi) ? (temp != 0) : (LO < midhi))
- HI += 1;
- HI += VH4_8(mid);
- if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; }
- }
- }
+ do_dmult (SD_, TRX, TRY);
}
-11101,xxx,yyy,11101:RR:16::DMULTU
+11101,3.RX,3.RY,11101:RR:16,64::DMULTU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Multiplication");
- {
- unsigned64 mid;
- unsigned64 midhi;
- unsigned64 temp;
- LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
- HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
- mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
- midhi = SET64HI(VL4_8(mid));
- temp = (LO + midhi);
- if ((temp == midhi) ? (LO != 0) : (temp < midhi))
- HI += 1;
- HI += VH4_8(mid);
- mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
- midhi = SET64HI(VL4_8(mid));
- LO = (temp + midhi);
- if ((LO == midhi) ? (temp != 0) : (LO < midhi))
- HI += 1;
- HI += VH4_8(mid);
- }
- }
+ do_dmultu (SD_, TRX, TRY);
}
-11101,xxx,yyy,11110:RR:16::DDIV
+11101,3.RX,3.RY,11110:RR:16,64::DDIV
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Division");
- {
- word64 d1 = op1;
- word64 d2 = op2;
- if (d2 == 0)
- {
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
- }
- else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
- {
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
- }
- else
- {
- LO = (d1 / d2);
- HI = (d1 % d2);
- }
- }
- }
+ do_ddiv (SD_, TRX, TRY);
}
-11101,xxx,yyy,11111:RR:16::DDIVU
+11101,3.RX,3.RY,11111:RR:16,64::DDIVU
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Division");
- {
- unsigned64 d1 = op1;
- unsigned64 d2 = op2;
- if (d2 == 0)
- {
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
- }
- else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
- {
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
- }
- else
- {
- LO = (d1 / d2);
- HI = (d1 % d2);
- }
- }
- }
+ do_ddivu (SD_, TRX, TRY);
}
// Jump and Branch Instructions
-// JALX
-// JAL
-00011,aaaaaaaaaaa:I:16::JAL
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- unsigned_word op1 = (instruction >> 0) & 0x7ff;
- {
- address_word paddr;
- int uncached;
- if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL))
- {
- unsigned64 memval;
- unsigned int reverse = (ReverseEndian ? 3 : 0);
- unsigned int bigend = (BigEndianCPU ? 3 : 0);
- unsigned int byte;
- paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1)));
- LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL);
- byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1));
- memval = (memval >> (8 * byte)) & 0xffff;
- op1 = (((op1 & 0x1f) << 23)
- | ((op1 & 0x3e0) << 13)
- | (memval << 2));
- if ((instruction & 0x400) == 0)
- op1 |= 1;
- PC += 2;
- }
- }
- op1 |= PC & ~ (unsigned64) 0x0fffffff;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int destreg = 31;
- GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
- /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
- so we just truncate it to 32 bits here. */
- op1 = VL4_8(op1);
- /* NOTE: The jump occurs AFTER the next instruction has been executed */
- DELAY_SLOT op1;
- JALDELAYSLOT();
- }
-}
-
-
-11101,xxx,00000000:RR:16::JR
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
- so we just truncate it to 32 bits here. */
- op1 = VL4_8(op1);
- /* NOTE: The jump occurs AFTER the next instruction has been executed */
- DELAY_SLOT op1;
- DELAYSLOT();
- }
-}
-
-
-1110100000100000,r:RR:16::JRRA
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = 31;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
- so we just truncate it to 32 bits here. */
- op1 = VL4_8(op1);
- /* NOTE: The jump occurs AFTER the next instruction has been executed */
- DELAY_SLOT op1;
- DELAYSLOT();
- }
-}
-
-
-11101,xxx,01000000,R:RR:16::JALR
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = 31;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
- /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
- so we just truncate it to 32 bits here. */
- op1 = VL4_8(op1);
- /* NOTE: The jump occurs AFTER the next instruction has been executed */
- DELAY_SLOT op1;
- DELAYSLOT();
- }
-}
-
-
-00100,xxx,pppppppp,z:RI:16::BEQZ
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op2 = 0;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
+
+// Issue instruction in delay slot of branch
+:function:::address_word:delayslot16:address_word target
+{
+ instruction_word delay_insn;
+ sim_events_slip (SD, 1);
+ DSPC = CIA; /* save current PC somewhere */
+ CIA = CIA + 2; /* NOTE: mips16 */
+ STATE |= simDELAYSLOT;
+ delay_insn = IMEM16 (CIA); /* NOTE: mips16 */
+ idecode_issue (CPU_, delay_insn, (CIA));
+ STATE &= ~simDELAYSLOT;
+ return target;
+}
+
+// compute basepc dependant on us being in a delay slot
+:function:::address_word:basepc:
+{
+ if (STATE & simDELAYSLOT)
{
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
+ return DSPC; /* return saved address of preceeding jmp */
}
else
{
- if (offset >= 0x80)
- offset -= 0x100;
+ return CIA;
}
- offset *= 2;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 == op2);
- if (condition)
- PC = PC + offset;
- }
}
-00101,xxx,pppppppp,z:RI:16::BNEZ
+// JAL
+00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JAL
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op2 = 0;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (offset >= 0x80)
- offset -= 0x100;
- }
- offset *= 2;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 != op2);
- if (condition)
- PC = PC + offset;
- }
+ NIA = delayslot16 (SD_,
+ (LSMASKED (NIA, 31, 26)
+ | LSINSERTED (IMM_25_21, 25, 21)
+ | LSINSERTED (IMM_20_16, 20, 16)
+ | LSINSERTED (IMMED_15_0, 15, 0)));
}
-01100000,pppppppp,t,z:I8:16::BTEQZ
+// JALX
+00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JALX
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 24;
- signed_word op2 = 0;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (offset >= 0x80)
- offset -= 0x100;
- }
- offset *= 2;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 == op2);
- if (condition)
- PC = PC + offset;
- }
+ NIA = delayslot16 (SD_,
+ (LSMASKED (NIA, 31, 26)
+ | LSINSERTED (IMM_25_21, 25, 21)
+ | LSINSERTED (IMM_20_16, 20, 16)
+ | LSINSERTED (IMMED_15_0, 15, 0)));
+ NIA = NIA ^ 1;
}
-01100001,pppppppp,t,z:I8:16::BTNEZ
+11101,3.RX,000,00000:RR:16::JR
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 24;
- signed_word op2 = 0;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (offset >= 0x80)
- offset -= 0x100;
- }
- offset *= 2;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 != op2);
- if (condition)
- PC = PC + offset;
- }
+ NIA = delayslot16 (SD_, GPR[TRX]);
}
-00010,qqqqqqqqqqq,z,Z:I:16::B
+11101,000,001,00000:RR:16::JRRA
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0x7ff;
- signed_word op2 = 0;
- signed_word op1 = 0;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (offset >= 0x400)
- offset -= 0x800;
- }
- offset *= 2;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 == op2);
- if (condition)
- PC = PC + offset;
- }
+ NIA = delayslot16 (SD_, RA);
}
-// Special Instructions
+11101,3.RX,010,00000:RR:16::JALR
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ RA = NIA + 2;
+ NIA = delayslot16 (SD_, GPR[TRX]);
+}
-// See the front of the mips16 doc
-11110,eeeeeeeeeee:I:16::EXTEND
+00100,3.RX,8.IMMED:RI:16::BEQZ
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ if (GPR[RX] == 0)
+ NIA = (NIA + (EXTEND8 (IMMED) << 2));
+}
+
+
+00101,3.RX,8.IMMED:RI:16::BNEZ
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ if (GPR[RX] != 0)
+ NIA = (NIA + (EXTEND8 (IMMED) << 2));
+}
+
+
+01100,000,8.IMMED:I8:16::BTEQZ
+*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ if (T8 == 0)
+ NIA = (NIA + (EXTEND8 (IMMED) << 2));
+}
+
+
+01100,001,8.IMMED:I8:16::BTNEZ
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int ext = (instruction >> 0) & 0x7ff;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- extendval = ext;
- have_extendval = 1;
- }
+ if (T8 != 0)
+ NIA = (NIA + (EXTEND8 (IMMED) << 2));
}
-01100,******,00101:RR:16::BREAK
+00010,11.IMMED:I:16::B
*mips16:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- SignalException(BreakPoint,instruction);
- }
+ NIA = (NIA + (EXTEND8 (IMMED) << 2));
}
+
+// Special Instructions
+
+
+// See the front of the mips16 doc
+// -> FIXME need this for most instructions
+// 11110,eeeeeeeeeee:I:16::EXTEND
+// *mips16:
+// // start-sanitize-tx19
+// *tx19:
+// // end-sanitize-tx19
+
+
+// 11101,3.RX,3.RY,00101:RR:16::BREAK
+// *mips16:
+// // start-sanitize-tx19
+// *tx19:
+// // end-sanitize-tx19
diff --git a/sim/mips/m16run.c b/sim/mips/m16run.c
new file mode 100644
index 0000000..da3691c
--- /dev/null
+++ b/sim/mips/m16run.c
@@ -0,0 +1,73 @@
+/* This file is part of the program psim.
+
+ Copyright (C) 1998, Andrew Cagney <cagney@highland.com.au>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ */
+
+#include "sim-main.h"
+#include "m16_idecode.h"
+#include "m32_idecode.h"
+#include "bfd.h"
+
+
+#define SD sd
+#define CPU cpu
+
+void
+sim_engine_run (SIM_DESC sd,
+ int next_cpu_nr,
+ int nr_cpus, /* ignore */
+ int siggnal) /* ignore */
+{
+ sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr);
+ address_word cia = CIA_GET (cpu);
+
+ while (1)
+ {
+ address_word nia;
+
+#if defined (ENGINE_ISSUE_PREFIX_HOOK)
+ ENGINE_ISSUE_PREFIX_HOOK ();
+#endif
+
+ if ((cia & 1))
+ {
+ m16_instruction_word instruction_0 = IMEM16 (cia);
+ nia = m16_idecode_issue (sd, instruction_0, cia);
+ }
+ else
+ {
+ m32_instruction_word instruction_0 = IMEM32 (cia);
+ nia = m32_idecode_issue (sd, instruction_0, cia);
+ }
+
+#if defined (ENGINE_ISSUE_POSTFIX_HOOK)
+ ENGINE_ISSUE_POSTFIX_HOOK ();
+#endif
+
+ /* Update the instruction address */
+ cia = nia;
+
+ /* process any events */
+ if (sim_events_tick (sd))
+ {
+ CIA_SET (CPU, cia);
+ sim_events_process (sd);
+ }
+
+ }
+}
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 4a1103c..ea39430 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -78,6 +78,7 @@
//
+
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -102,6 +103,7 @@
}
+
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, IMMEDIATE"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -126,6 +128,13 @@
}
+
+:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
+{
+ signed32 temp = GPR[rs] + EXTEND16 (immediate);
+ GPR[rt] = EXTEND32 (temp);
+}
+
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
"addu r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -144,11 +153,17 @@
*tx19:
// end-sanitize-tx19
{
- signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
- GPR[RT] = EXTEND32 (temp);
+ do_addiu (SD_, RS, RT, IMMEDIATE);
}
+
+:function:::void:do_addu:int rs, int rt, int rd
+{
+ signed32 temp = GPR[rs] + GPR[rt];
+ GPR[rd] = EXTEND32 (temp);
+}
+
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
"addu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -167,11 +182,16 @@
*tx19:
// end-sanitize-tx19
{
- signed32 temp = GPR[RS] + GPR[RT];
- GPR[RD] = EXTEND32 (temp);
+ do_addu (SD_, RS, RT, RD);
}
+
+:function:::void:do_and:int rs, int rt, int rd
+{
+ GPR[rd] = GPR[rs] & GPR[rt];
+}
+
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -190,10 +210,11 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] & GPR[RT];
+ do_and (SD_, RS, RT, RD);
}
+
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
"and r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -216,6 +237,7 @@
}
+
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -240,6 +262,7 @@
}
+
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
"beql r<RS>, r<RT>, <OFFSET>"
*mipsII:
@@ -268,6 +291,7 @@
}
+
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -292,6 +316,7 @@
}
+
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -317,6 +342,7 @@
}
+
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
"bgezall r<RS>, <OFFSET>"
*mipsII:
@@ -348,6 +374,7 @@
}
+
000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
@@ -376,6 +403,7 @@
}
+
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -400,6 +428,7 @@
}
+
010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
"bgtzl r<RS>, <OFFSET>"
*mipsII:
@@ -430,6 +459,7 @@
}
+
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -456,6 +486,7 @@
}
+
010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
@@ -484,6 +515,7 @@
}
+
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -508,6 +540,7 @@
}
+
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -535,6 +568,7 @@
}
+
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
"bltzall r<RS>, <OFFSET>"
*mipsII:
@@ -564,6 +598,7 @@
}
+
000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
"bltzl r<RS>, <OFFSET>"
*mipsII:
@@ -594,6 +629,7 @@
}
+
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -618,6 +654,7 @@
}
+
010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
"bnel r<RS>, r<RT>, <OFFSET>"
*mipsII:
@@ -646,6 +683,7 @@
}
+
000000,20.CODE,001101:SPECIAL:32::BREAK
"break"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -668,6 +706,7 @@
}
+
0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
"cop<ZZ> <COP_FUN>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -683,6 +722,7 @@
}
+
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
"dadd r<RD>, r<RS>, r<RT>"
*mipsIII:
@@ -708,6 +748,7 @@
}
+
011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
"daddi r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
@@ -732,6 +773,12 @@
}
+
+:function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
+{
+ GPR[rt] = GPR[rs] + EXTEND16 (immediate);
+}
+
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
"daddu r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
@@ -750,10 +797,16 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
+ do_daddiu (SD_, RS, RT, IMMEDIATE);
}
+
+:function:::void:do_daddu:int rs, int rt, int rd
+{
+ GPR[rd] = GPR[rs] + GPR[rt];
+}
+
000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
"daddu r<RD>, r<RS>, r<RT>"
*mipsIII:
@@ -772,32 +825,17 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] + GPR[RT];
+ do_daddu (SD_, RS, RT, RD);
}
-000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
-"ddiv r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+
+:function:64::void:do_ddiv:int rs, int rt
{
CHECKHILO ("Division");
{
- signed64 n = GPR[RS];
- signed64 d = GPR[RT];
+ signed64 n = GPR[rs];
+ signed64 d = GPR[rt];
if (d == 0)
{
LO = SIGNED64 (0x8000000000000000);
@@ -816,10 +854,8 @@
}
}
-
-
-000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
-"ddivu r<RS>, r<RT>"
+000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
+"ddiv r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*vr5000:
@@ -829,14 +865,24 @@
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
+ do_ddiv (SD_, RS, RT);
+}
+
+
+
+:function:64::void:do_ddivu:int rs, int rt
+{
CHECKHILO ("Division");
{
- unsigned64 n = GPR[RS];
- unsigned64 d = GPR[RT];
+ unsigned64 n = GPR[rs];
+ unsigned64 d = GPR[rt];
if (d == 0)
{
LO = SIGNED64 (0x8000000000000000);
@@ -850,10 +896,10 @@
}
}
-
-000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
-"div r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
+"ddivu r<RS>, r<RT>"
+*mipsIII:
+*mipsIV:
*vr5000:
// start-sanitize-vr4320
*vr4320:
@@ -861,18 +907,21 @@
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
+ do_ddivu (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_div:int rs, int rt
+{
CHECKHILO("Division");
{
- signed32 n = GPR[RS];
- signed32 d = GPR[RT];
+ signed32 n = GPR[rs];
+ signed32 d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
@@ -891,9 +940,8 @@
}
}
-
-000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
-"divu r<RS>, r<RT>"
+000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
+"div r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
// start-sanitize-vr4320
@@ -910,10 +958,17 @@
*tx19:
// end-sanitize-tx19
{
+ do_div (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_divu:int rs, int rt
+{
CHECKHILO ("Division");
{
- unsigned32 n = GPR[RS];
- unsigned32 d = GPR[RT];
+ unsigned32 n = GPR[rs];
+ unsigned32 d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
@@ -927,8 +982,30 @@
}
}
+000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
+"divu r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+ do_divu (SD_, RS, RT);
+}
+
-:function:::void:do_dmult:int rs, int rt, int rd, int signed_p
+
+:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
unsigned64 lo;
unsigned64 hi;
@@ -986,6 +1063,10 @@
GPR[rd] = lo;
}
+:function:::void:do_dmult:int rs, int rt, int rd
+{
+ do_dmultx (SD_, rs, rt, rd, 1);
+}
000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
@@ -997,7 +1078,7 @@
*vr4320:
// end-sanitize-vr4320
{
- do_dmult (SD_, RS, RT, 0, 1);
+ do_dmult (SD_, RS, RT, 0);
}
000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
@@ -1008,11 +1089,16 @@
*vr5400:
// end-sanitize-vr5400
{
- do_dmult (SD_, RS, RT, RD, 1);
+ do_dmult (SD_, RS, RT, RD);
}
+:function:::void:do_dmultu:int rs, int rt, int rd
+{
+ do_dmultx (SD_, rs, rt, rd, 0);
+}
+
000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
*mipsIII,mipsIV:
@@ -1023,7 +1109,7 @@
*vr4320:
// end-sanitize-vr4320
{
- do_dmult (SD_, RS, RT, 0, 0);
+ do_dmultu (SD_, RS, RT, 0);
}
000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
@@ -1034,7 +1120,7 @@
*vr5400:
// end-sanitize-vr5400
{
- do_dmult (SD_, RS, RT, RD, 0);
+ do_dmultu (SD_, RS, RT, RD);
}
@@ -1085,6 +1171,7 @@
}
+
000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
*mipsIII:
@@ -1108,6 +1195,7 @@
}
+
00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
@@ -1154,6 +1242,12 @@
}
+:function:::void:do_srav:int rs, int rt, int rd
+{
+ int s = MASKED64 (GPR[rs], 5, 0);
+ GPR[rd] = ((signed64) GPR[rt]) >> s;
+}
+
000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
"dsra32 r<RT>, r<RD>, r<RS>"
*mipsIII:
@@ -1172,8 +1266,7 @@
*tx19:
// end-sanitize-tx19
{
- int s = MASKED64 (GPR[RS], 5, 0);
- GPR[RD] = ((signed64) GPR[RT]) >> s;
+ do_srav (SD_, RS, RT, RD);
}
@@ -1270,6 +1363,11 @@
}
+:function:::void:do_dsubu:int rs, int rt, int rd
+{
+ GPR[rd] = GPR[rs] - GPR[rt];
+}
+
000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
*mipsIII:
@@ -1288,7 +1386,7 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] - GPR[RT];
+ do_dsubu (SD_, RS, RT, RD);
}
@@ -1883,6 +1981,14 @@
}
+:function:::void:do_mfhi:int rd
+{
+ GPR[rd] = HI;
+#if 0
+ HIACCESS = 3;
+#endif
+}
+
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -1901,13 +2007,19 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = HI;
+ do_mfhi (SD_, RD);
+}
+
+
+
+:function:::void:do_mflo:int rd
+{
+ GPR[rd] = LO;
#if 0
- HIACCESS = 3;
+ LOACCESS = 3; /* 3rd instruction will be safe */
#endif
}
-
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -1926,13 +2038,11 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = LO;
-#if 0
- LOACCESS = 3; /* 3rd instruction will be safe */
-#endif
+ do_mflo (SD_, RD);
}
+
000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
@@ -1952,6 +2062,7 @@
}
+
000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
@@ -1971,6 +2082,7 @@
}
+
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2000,6 +2112,7 @@
}
+
000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2029,6 +2142,19 @@
}
+
+:function:::void:do_mult:int rs, int rt, int rd
+{
+ signed64 prod;
+ CHECKHILO ("Multiplication");
+ prod = (((signed64)(signed32) GPR[rs])
+ * ((signed64)(signed32) GPR[rt]));
+ LO = EXTEND32 (VL4_8 (prod));
+ HI = EXTEND32 (VH4_8 (prod));
+ if (rd != 0)
+ GPR[rd] = LO;
+}
+
000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2036,12 +2162,7 @@
*vr4320:
// end-sanitize-vr4320
{
- signed64 prod;
- CHECKHILO ("Multiplication");
- prod = (((signed64)(signed32) GPR[RS])
- * ((signed64)(signed32) GPR[RT]));
- LO = EXTEND32 (VL4_8 (prod));
- HI = EXTEND32 (VH4_8 (prod));
+ do_mult (SD_, RS, RT, 0);
}
@@ -2059,17 +2180,22 @@
*tx19:
// end-sanitize-tx19
{
- signed64 prod;
+ do_mult (SD_, RS, RT, RD);
+}
+
+
+:function:::void:do_multu:int rs, int rt, int rd
+{
+ unsigned64 prod;
CHECKHILO ("Multiplication");
- prod = (((signed64)(signed32) GPR[RS])
- * ((signed64)(signed32) GPR[RT]));
+ prod = (((unsigned64)(unsigned32) GPR[rs])
+ * ((unsigned64)(unsigned32) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
- if (RD != 0)
- GPR[RD] = LO;
+ if (rd != 0)
+ GPR[rd] = LO;
}
-
000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2077,13 +2203,9 @@
*vr4320:
// end-sanitize-vr4320
{
- unsigned64 prod;
- CHECKHILO ("Multiplication");
- prod = (((unsigned64)(unsigned32) GPR[RS])
- * ((unsigned64)(unsigned32) GPR[RT]));
- LO = EXTEND32 (VL4_8 (prod));
- HI = EXTEND32 (VH4_8 (prod));
+ do_multu (SD_, RS, RT, 0);
}
+
000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
"multu r<RD>, r<RS>, r<RT>"
*vr5000:
@@ -2098,17 +2220,15 @@
*tx19:
// end-sanitize-tx19
{
- unsigned64 prod;
- CHECKHILO ("Multiplication");
- prod = (((unsigned64)(unsigned32) GPR[RS])
- * ((unsigned64)(unsigned32) GPR[RT]));
- LO = EXTEND32 (VL4_8 (prod));
- HI = EXTEND32 (VH4_8 (prod));
- if (RD != 0)
- GPR[RD] = LO;
+ do_multu (SD_, RS, RT, 0);
}
+:function:::void:do_nor:int rs, int rt, int rd
+{
+ GPR[rd] = ~ (GPR[rs] | GPR[rt]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2127,10 +2247,15 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = ~ (GPR[RS] | GPR[RT]);
+ do_nor (SD_, RS, RT, RD);
}
+:function:::void:do_or:int rs, int rt, int rd
+{
+ GPR[rd] = (GPR[rs] | GPR[rt]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2149,7 +2274,7 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = (GPR[RS] | GPR[RT]);
+ do_or (SD_, RS, RT, RD);
}
@@ -2455,6 +2580,12 @@
}
+:function:::void:do_sll:int rt, int rd, int shift
+{
+ unsigned32 temp = (GPR[rt] << shift);
+ GPR[rd] = EXTEND32 (temp);
+}
+
00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2473,12 +2604,17 @@
*tx19:
// end-sanitize-tx19
{
- int s = SHIFT;
- unsigned32 temp = (GPR[RT] << s);
- GPR[RD] = EXTEND32 (temp);
+ do_sll (SD_, RT, RD, SHIFT);
}
+:function:::void:do_sllv:int rs, int rt, int rd
+{
+ int s = MASKED (GPR[rs], 4, 0);
+ unsigned32 temp = (GPR[rt] << s);
+ GPR[rd] = EXTEND32 (temp);
+}
+
000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2497,12 +2633,15 @@
*tx19:
// end-sanitize-tx19
{
- int s = MASKED (GPR[RS], 4, 0);
- unsigned32 temp = (GPR[RT] << s);
- GPR[RD] = EXTEND32 (temp);
+ do_sllv (SD_, RS, RT, RD);
}
+:function:::void:do_slt:int rs, int rt, int rd
+{
+ GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
+}
+
000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2521,10 +2660,15 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
+ do_slt (SD_, RS, RT, RD);
}
+:function:::void:do_slti:int rs, int rt, unsigned16 immediate
+{
+ GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
+}
+
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
"slti r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2543,10 +2687,15 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
+ do_slti (SD_, RS, RT, IMMEDIATE);
}
+:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
+{
+ GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
+}
+
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2565,7 +2714,14 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
+ do_sltiu (SD_, RS, RT, IMMEDIATE);
+}
+
+
+
+:function:::void:do_sltu:int rs, int rt, int rd
+{
+ GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
}
000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
@@ -2586,10 +2742,16 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
+ do_sltiu (SD_, RS, RT, RD);
}
+:function:::void:do_sra:int rt, int rd, int shift
+{
+ signed32 temp = (signed32) GPR[rt] >> shift;
+ GPR[rd] = EXTEND32 (temp);
+}
+
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
"sra r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2608,9 +2770,7 @@
*tx19:
// end-sanitize-tx19
{
- int s = SHIFT;
- signed32 temp = (signed32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_sra (SD_, RT, RD, SHIFT);
}
@@ -2638,6 +2798,12 @@
}
+:function:::void:do_srl:int rt, int rd, int shift
+{
+ unsigned32 temp = (unsigned32) GPR[rt] >> shift;
+ GPR[rd] = EXTEND32 (temp);
+}
+
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
"srl r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2656,12 +2822,17 @@
*tx19:
// end-sanitize-tx19
{
- int s = SHIFT;
- unsigned32 temp = (unsigned32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_srl (SD_, RT, RD, SHIFT);
}
+:function:::void:do_srlv:int rs, int rt, int rd
+{
+ int s = MASKED (GPR[rs], 4, 0);
+ unsigned32 temp = (unsigned32) GPR[rt] >> s;
+ GPR[rd] = EXTEND32 (temp);
+}
+
000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2680,9 +2851,7 @@
*tx19:
// end-sanitize-tx19
{
- int s = MASKED (GPR[RS], 4, 0);
- unsigned32 temp = (unsigned32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_srlv (SD_, RS, RT, RD);
}
@@ -2710,6 +2879,12 @@
}
+:function:::void:do_subu:int rs, int rt, int rd
+{
+ signed32 temp = GPR[rs] - GPR[rt];
+ GPR[rd] = EXTEND32 (temp);
+}
+
000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2728,7 +2903,7 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
+ do_subu (SD_, RS, RT, RD);
}
@@ -3199,6 +3374,11 @@
}
+:function:::void:do_xor:int rs, int rt, int rd
+{
+ GPR[rd] = GPR[rs] ^ GPR[rt];
+}
+
000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -3217,10 +3397,15 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] ^ GPR[RT];
+ do_xor (SD_, RS, RT, RD);
}
+:function:::void:do_xori:int rs, int rt, unsigned16 immediate
+{
+ GPR[rt] = GPR[rs] ^ immediate;
+}
+
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
"xori r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -3239,7 +3424,7 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RT] = GPR[RS] ^ IMMEDIATE;
+ do_xori (SD_, RS, RT, IMMEDIATE);
}
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index af9378a..2a80742 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -456,8 +456,6 @@ struct _sim_cpu {
NIA = CIA + 8; \
} while (0)
-
-
/* State of the simulator */
unsigned int state;
unsigned int dsstate;
@@ -574,8 +572,12 @@ struct _sim_cpu {
#define A1 (REGISTERS[5])
#define A2 (REGISTERS[6])
#define A3 (REGISTERS[7])
-#define SP (REGISTERS[29])
-#define RA (REGISTERS[31])
+#define T8IDX 24
+#define T8 (REGISTERS[T8IDX])
+#define SPIDX 29
+#define SP (REGISTERS[SPIDX])
+#define RAIDX 31
+#define RA (REGISTERS[RAIDX])
/* Keep the current format state for each register: */
FP_formats fpr_state[32];
@@ -865,7 +867,7 @@ prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
unsigned16 ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
-#define IMEM16(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
+#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
generated by cgit v1.1 at 2024-12-12 04:05:09 +0000