2002-06-03 Chris Demetriou <cgd@broadcom.com>

            Ed Satterthwaite  <ehs@broadcom.com>

	* configure.in (mipsisa64sb1*-*-*): New target for supporting
	Broadcom SiByte SB-1 processor configurations.
	* configure: Regenerate.
	* sb1.igen: New file.
	* mips.igen: Include sb1.igen.
	(sb1): New model.
	* Makefile.in (IGEN_INCLUDE): Add sb1.igen.
	* mdmx.igen: Add "sb1" model to all appropriate functions and
	instructions.
	* mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
	(ob_func, ob_acc): Reference the above.
	(qh_acc): Adjust to keep the same size as ob_acc.
	* sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
	(MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.

9 files changed, 316 insertions, 19 deletions

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 8e220c7..f237863 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,4 +1,22 @@
 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
+            Ed Satterthwaite  <ehs@broadcom.com>
+
+	* configure.in (mipsisa64sb1*-*-*): New target for supporting
+	Broadcom SiByte SB-1 processor configurations.
+	* configure: Regenerate.
+	* sb1.igen: New file.
+	* mips.igen: Include sb1.igen.
+	(sb1): New model.
+	* Makefile.in (IGEN_INCLUDE): Add sb1.igen.
+	* mdmx.igen: Add "sb1" model to all appropriate functions and
+	instructions.
+	* mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
+	(ob_func, ob_acc): Reference the above.
+	(qh_acc): Adjust to keep the same size as ob_acc.
+	* sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
+	(MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
+
+2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 
 	* Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 
diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in
index b1d2ad7..f4604c0 100644
--- a/sim/mips/Makefile.in
+++ b/sim/mips/Makefile.in
@@ -84,6 +84,7 @@ M16_DC=$(srcdir)/m16.dc
 IGEN_INCLUDE=\
 	$(srcdir)/m16.igen \
 	$(srcdir)/mdmx.igen \
+	$(srcdir)/sb1.igen \
 	$(srcdir)/tx.igen \
 	$(srcdir)/vr.igen \
 
diff --git a/sim/mips/configure b/sim/mips/configure
index e5f427e..2a9d8b9 100755
--- a/sim/mips/configure
+++ b/sim/mips/configure
@@ -4023,6 +4023,10 @@ case "${target}" in
 		        sim_igen_machine="-M mips32"
 			sim_igen_filter="32,f"
 			;;
+  mipsisa64sb1*-*-*)	sim_gen=IGEN
+		        sim_igen_machine="-M mips64,sb1"
+			sim_igen_filter="32,64,f"
+			;;
   mipsisa64*-*-*)	sim_gen=IGEN
 		        sim_igen_machine="-M mips64"
 			sim_igen_filter="32,64,f"
@@ -4132,7 +4136,7 @@ esac
 # Uses ac_ vars as temps to allow command line to override cache and checks.
 # --without-x overrides everything else, but does not touch the cache.
 echo $ac_n "checking for X""... $ac_c" 1>&6
-echo "configure:4136: checking for X" >&5
+echo "configure:4140: checking for X" >&5
 
 # Check whether --with-x or --without-x was given.
 if test "${with_x+set}" = set; then
@@ -4194,12 +4198,12 @@ if test "$ac_x_includes" = NO; then
 
   # First, try using that file with no special directory specified.
 cat > conftest.$ac_ext <<EOF
-#line 4198 "configure"
+#line 4202 "configure"
 #include "confdefs.h"
 #include <$x_direct_test_include>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:4203: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:4207: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -4268,14 +4272,14 @@ if test "$ac_x_libraries" = NO; then
   ac_save_LIBS="$LIBS"
   LIBS="-l$x_direct_test_library $LIBS"
 cat > conftest.$ac_ext <<EOF
-#line 4272 "configure"
+#line 4276 "configure"
 #include "confdefs.h"
 
 int main() {
 ${x_direct_test_function}()
 ; return 0; }
 EOF
-if { (eval echo configure:4279: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:4283: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   LIBS="$ac_save_LIBS"
 # We can link X programs with no special library path.
@@ -4368,17 +4372,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h
 do
 ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:4372: checking for $ac_hdr" >&5
+echo "configure:4376: checking for $ac_hdr" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 4377 "configure"
+#line 4381 "configure"
 #include "confdefs.h"
 #include <$ac_hdr>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:4382: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:4386: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -4405,7 +4409,7 @@ fi
 done
 
 echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
-echo "configure:4409: checking for fabs in -lm" >&5
+echo "configure:4413: checking for fabs in -lm" >&5
 ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
 if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -4413,7 +4417,7 @@ else
   ac_save_LIBS="$LIBS"
 LIBS="-lm  $LIBS"
 cat > conftest.$ac_ext <<EOF
-#line 4417 "configure"
+#line 4421 "configure"
 #include "confdefs.h"
 /* Override any gcc2 internal prototype to avoid an error.  */
 /* We use char because int might match the return type of a gcc2
@@ -4424,7 +4428,7 @@ int main() {
 fabs()
 ; return 0; }
 EOF
-if { (eval echo configure:4428: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:4432: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_lib_$ac_lib_var=yes"
 else
@@ -4454,12 +4458,12 @@ fi
 for ac_func in aint anint sqrt
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:4458: checking for $ac_func" >&5
+echo "configure:4462: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 4463 "configure"
+#line 4467 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -4482,7 +4486,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:4486: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:4490: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
diff --git a/sim/mips/configure.in b/sim/mips/configure.in
index d8c4023..bb71308 100644
--- a/sim/mips/configure.in
+++ b/sim/mips/configure.in
@@ -128,6 +128,10 @@ case "${target}" in
 		        sim_igen_machine="-M mips32"
 			sim_igen_filter="32,f"
 			;;
+  mipsisa64sb1*-*-*)	sim_gen=IGEN
+		        sim_igen_machine="-M mips64,sb1"
+			sim_igen_filter="32,64,f"
+			;;
   mipsisa64*-*-*)	sim_gen=IGEN
 		        sim_igen_machine="-M mips64"
 			sim_igen_filter="32,64,f"
diff --git a/sim/mips/mdmx.c b/sim/mips/mdmx.c
index 2b08922..96abe1d 100644
--- a/sim/mips/mdmx.c
+++ b/sim/mips/mdmx.c
@@ -250,7 +250,6 @@ MsgnQH(signed16 ts, signed16 tt)
   return t;
 }
 
-
 static signed16
 SRAQH(signed16 ts, signed16 tt)
 {
@@ -259,6 +258,21 @@ SRAQH(signed16 ts, signed16 tt)
 }
 
 
+/* "pabsdiff" and "pavg" are defined only for OB format.  */
+
+static unsigned8
+AbsDiffOB(unsigned8 ts, unsigned8 tt)
+{
+  return (ts >= tt ? ts - tt : tt - ts);
+}
+
+static unsigned8
+AvgOB(unsigned8 ts, unsigned8 tt)
+{
+  return ((unsigned32)ts + (unsigned32)tt + 1) >> 1;
+}
+
+
 /* Dispatch tables for operations that update a CPR.  */
 
 static const QH_FUNC qh_func[] = {
@@ -270,7 +284,7 @@ static const QH_FUNC qh_func[] = {
 static const OB_FUNC ob_func[] = {
   AndOB,  NorOB,  OrOB,   XorOB, SLLOB, SRLOB,
   AddOB,  SubOB,  MinOB,  MaxOB,
-  MulOB,  NULL,   NULL,   NULL, NULL
+  MulOB,  NULL,   NULL,   AbsDiffOB, AvgOB
 };
 
 /* Auxiliary functions for CPR updates.  */
@@ -743,17 +757,26 @@ AccSubLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
   *a = (signed24)ts - (signed24)tt;
 }
 
+static void
+AccAbsDiffOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+{
+  unsigned8 t = (ts >= tt ? ts - tt : tt - ts);
+  *a += (signed24)t;
+}
+
 
 /* Dispatch tables for operations that update a CPR.  */
 
 static const QH_ACC qh_acc[] = {
   AccAddAQH, AccAddAQH, AccMulAQH, AccMulLQH,
-  SubMulAQH, SubMulLQH, AccSubAQH, AccSubLQH
+  SubMulAQH, SubMulLQH, AccSubAQH, AccSubLQH,
+  NULL
 };
 
 static const OB_ACC ob_acc[] = {
   AccAddAOB, AccAddLOB, AccMulAOB, AccMulLOB,
-  SubMulAOB, SubMulLOB, AccSubAOB, AccSubLOB
+  SubMulAOB, SubMulLOB, AccSubAOB, AccSubLOB,
+  AccAbsDiffOB
 };
 
 
diff --git a/sim/mips/mdmx.igen b/sim/mips/mdmx.igen
index ddc075c..f286e3b 100644
--- a/sim/mips/mdmx.igen
+++ b/sim/mips/mdmx.igen
@@ -32,6 +32,10 @@
 //  Similarly, for the single-bit fields which differentiate between
 //  formats (FMTOP), 0 is OB format and 1 is QH format.
 
+//  If you change this file to add instructions, please make sure that model
+//  "sb1" configurations still build, and that you've added no new
+//  instructions to the "sb1" model.
+
 
 // Helper:
 //
@@ -93,6 +97,7 @@
 
 :%s::::FMTSEL:int fmtsel
 *mdmx:
+*sb1:
 {
   if ((fmtsel & 0x1) == 0)
     return "ob";
@@ -105,6 +110,7 @@
 
 :%s::::FMTOP:int fmtop
 *mdmx:
+*sb1:
 {
   switch (fmtop)
     {
@@ -117,6 +123,7 @@
 
 :%s::::SHOP:int shop
 *mdmx:
+*sb1:
 {
   if ((shop & 0x11) == 0x00)
     switch ((shop >> 1) & 0x07)
@@ -146,6 +153,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,001011:MDMX:64::ADD.fmt
 "add.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -156,6 +164,7 @@
 011110,5.FMTSEL,5.VT,5.VS,0,0000,110111:MDMX:64::ADDA.fmt
 "adda.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -166,6 +175,7 @@
 011110,5.FMTSEL,5.VT,5.VS,1,0000,110111:MDMX:64::ADDL.fmt
 "addl.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -176,6 +186,7 @@
 011110,00,3.IMM,5.VT,5.VS,5.VD,0110,1.FMTOP,0:MDMX:64::ALNI.fmt
 "alni.%s<FMTOP> v<VD>, v<VS>, v<VT>, <IMM>"
 *mdmx:
+*sb1:
 {
   unsigned64 result;
   int s;
@@ -192,6 +203,7 @@
 011110,5.RS,5.VT,5.VS,5.VD,0110,1.FMTOP,1:MDMX:64::ALNV.fmt
 "alnv.%s<FMTOP> v<VD>, v<VS>, v<VT>, r<RS>"
 *mdmx:
+*sb1:
 {
   unsigned64 result;
   int s;
@@ -208,6 +220,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,001100:MDMX:64::AND.fmt
 "and.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -218,6 +231,7 @@
 011110,5.FMTSEL,5.VT,5.VS,00000,000001:MDMX:64::C.EQ.fmt
 "c.eq.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -228,6 +242,7 @@
 011110,5.FMTSEL,5.VT,5.VS,00000,000101:MDMX:64::C.LE.fmt
 "c.le.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -238,6 +253,7 @@
 011110,5.FMTSEL,5.VT,5.VS,00000,000100:MDMX:64::C.LT.fmt
 "c.lt.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -248,6 +264,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,000111:MDMX:64::MAX.fmt
 "max.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -258,6 +275,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,000110:MDMX:64::MIN.fmt
 "min.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -277,6 +295,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,110000:MDMX:64::MUL.fmt
 "mul.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -287,6 +306,7 @@
 011110,5.FMTSEL,5.VT,5.VS,0,0000,110011:MDMX:64::MULA.fmt
 "mula.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -297,6 +317,7 @@
 011110,5.FMTSEL,5.VT,5.VS,1,0000,110011:MDMX:64::MULL.fmt
 "mull.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -307,6 +328,7 @@
 011110,5.FMTSEL,5.VT,5.VS,0,0000,110010:MDMX:64::MULS.fmt
 "muls.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -317,6 +339,7 @@
 011110,5.FMTSEL,5.VT,5.VS,1,0000,110010:MDMX:64::MULSL.fmt
 "mulsl.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -327,6 +350,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,001111:MDMX:64::NOR.fmt
 "nor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -337,6 +361,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,001110:MDMX:64::OR.fmt
 "or.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -347,6 +372,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,000010:MDMX:64::PICKF.fmt
 "pickf.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -357,6 +383,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,000011:MDMX:64::PICKT.fmt
 "pickt.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -367,6 +394,7 @@
 011110,1000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.fmt
 "rach.%s<FMTOP> v<VD>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
@@ -377,6 +405,7 @@
 011110,0000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.fmt
 "racl.%s<FMTOP> v<VD>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
@@ -387,6 +416,7 @@
 011110,0100,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.fmt
 "racm.%s<FMTOP> v<VD>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
@@ -406,6 +436,7 @@
 011110,5.FMTSEL,5.VT,00000,5.VD,100001:MDMX:64::RNAU.fmt
 "rnau.%s<FMTSEL> v<VD>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -425,6 +456,7 @@
 011110,5.FMTSEL,5.VT,00000,5.VD,100010:MDMX:64::RNEU.fmt
 "rneu.%s<FMTSEL> v<VD>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -444,6 +476,7 @@
 011110,5.FMTSEL,5.VT,00000,5.VD,100000:MDMX:64::RZU.fmt
 "rzu.%s<FMTSEL> v<VD>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -454,6 +487,7 @@
 011110,5.SHOP,5.VT,5.VS,5.VD,011111:MDMX:64::SHFL.op.fmt
 "shfl.%s<SHOP> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, SHOP))
@@ -464,6 +498,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,010000:MDMX:64::SLL.fmt
 "sll.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -483,6 +518,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,010010:MDMX:64::SRL.fmt
 "srl.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -493,6 +529,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,001010:MDMX:64::SUB.fmt
 "sub.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -503,6 +540,7 @@
 011110,5.FMTSEL,5.VT,5.VS,0,0000,110110:MDMX:64::SUBA.fmt
 "suba.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -513,6 +551,7 @@
 011110,5.FMTSEL,5.VT,5.VS,1,0000,110110:MDMX:64::SUBL.fmt
 "subl.%s<FMTSEL> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
@@ -523,6 +562,7 @@
 011110,1000,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.fmt
 "wach.%s<FMTOP> v<VS>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
@@ -533,6 +573,7 @@
 011110,0000,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.fmt
 "wacl.%s<FMTOP> v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
@@ -543,6 +584,7 @@
 011110,5.FMTSEL,5.VT,5.VS,5.VD,001101:MDMX:64::XOR.fmt
 "xor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
 *mdmx:
+*sb1:
 {
   check_mdmx (SD_, instruction_0);
   if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 5416f06..b282602 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -65,6 +65,12 @@
 :model:::mips16:mips16:			// m16.igen (and m16.dc)
 :model:::mdmx:mdmx:			// mdmx.igen
 
+//  Vendor Extensions
+//
+//  Instructions specific to these extensions are in separate .igen files.
+//  Extensions add instructions on to a base ISA.
+:model:::sb1:sb1:			// sb1.igen
+
 
 // Pseudo instructions known by IGEN
 :internal::::illegal:
@@ -5057,6 +5063,7 @@
 
 :include:::m16.igen
 :include:::mdmx.igen
+:include:::sb1.igen
 :include:::tx.igen
 :include:::vr.igen
 
diff --git a/sim/mips/sb1.igen b/sim/mips/sb1.igen
new file mode 100644
index 0000000..6453670
--- /dev/null
+++ b/sim/mips/sb1.igen
@@ -0,0 +1,191 @@
+// -*- C -*-
+
+// Simulator definition for the Broadcom SiByte SB-1 CPU extensions.
+// Copyright (C) 2002 Free Software Foundation, Inc.
+// Contributed by Broadcom Corporation (SiByte).
+//
+// This file is part of GDB, the GNU debugger.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2, or (at your option)
+// any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License along
+// with this program; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+
+//  MDMX ASE Instructions
+//  ---------------------
+//
+//  The SB-1 implements the format OB subset of MDMX
+//  and has three additions (pavg, pabsdiff, pabsdifc).
+//  In addition, there are a couple of partial-decoding
+//  issues for the read/write accumulator instructions.
+//
+//  This code is structured so that mdmx.igen can be used by
+//  selecting the allowed instructions either via model, or by
+//  using check_mdmx_fmtsel and check_mdmx_fmtop to cause an
+//  exception if the instruction is not allowed.
+
+
+:function:::void:check_mdmx:instruction_word insn
+*sb1:
+{
+  if (!COP_Usable(1))
+    SignalExceptionCoProcessorUnusable(1);
+  if ((SR & status_MX) == 0)
+    SignalExceptionMDMX();
+  check_u64 (SD_, insn);
+}
+
+:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
+*sb1:
+{
+  switch (fmtsel & 0x03)
+    {
+    case 0x00:     /* ob */
+    case 0x02:
+      return 1;
+    case 0x01:     /* qh */
+    case 0x03:     /* UNPREDICTABLE */
+      SignalException (ReservedInstruction, insn);
+      return 0;
+    }
+  return 0;
+}
+
+:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
+*sb1:
+{
+  switch (fmtop & 0x01)
+    {
+    case 0x00:     /* ob */
+      return 1;
+    case 0x01:     /* qh */
+      SignalException (ReservedInstruction, insn);
+      return 0;
+    }
+  return 0;
+}
+
+
+011110,10,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.sb1.fmt
+"rach.?<X>.%s<FMTOP> v<VD>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
+  /* No op.  */
+}
+
+
+011110,00,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.sb1.fmt
+"racl.?<X>.%s<FMTOP> v<VD>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
+  /* No op.  */
+}
+
+
+011110,01,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.sb1.fmt
+"racm.?<X>.%s<FMTOP> v<VD>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
+  /* No op.  */
+}
+
+
+011110,2.X1!0!1!2,2.X2,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RAC.sb1.fmt
+"rac?<X1>.?<X2> v<VD>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
+  /* No op.  */
+}
+
+
+011110,10,2.X!0,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.sb1.fmt
+"wach.?<X>.%s<FMTOP> v<VS>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
+  /* No op.  */
+}
+
+
+011110,00,2.X!0,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.sb1.fmt
+"wacl.?<X>.%s<FMTOP> v<VS>,v<VT>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
+  /* No op.  */
+}
+
+
+011110,2.X1!0!2,2.X2,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WAC.sb1.fmt
+"wacl?<X1>.?<X2>.%s<FMTOP> v<VS>,v<VT>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
+  /* No op.  */
+}
+
+
+011110,5.FMTSEL,5.VT,5.VS,5.VD,001001:MDMX:64::PABSDIFF.fmt
+"pabsdiff.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  if (SR & status_SBX)
+    {
+      check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
+      StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
+    }
+  else
+    SignalException(ReservedInstruction, instruction_0);
+}
+
+
+011110,5.FMTSEL,5.VT,5.VS,00000,110101:MDMX:64::PABSDIFC.fmt
+"pabsdifc.%<FMTSEL> v<VS>,v<VT>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  if (SR & status_SBX)
+    {
+      check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
+      MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
+    }
+  else
+    SignalException(ReservedInstruction, instruction_0);
+}
+
+
+011110,5.FMTSEL,5.VT,5.VS,5.VD,001000:MDMX:64::PAVG.fmt
+"pavg.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
+*sb1:
+{
+  check_mdmx (SD_, instruction_0);
+  if (SR & status_SBX)
+    {
+      check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
+      StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
+    }
+  else
+    SignalException(ReservedInstruction, instruction_0);
+}
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 08d2e60..462606e 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -567,6 +567,8 @@ struct sim_state {
 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
+/* Bits reserved for implementations:  */
+#define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 
 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
@@ -743,7 +745,6 @@ typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 #define MX_VECT_XOR  (3)
 #define MX_VECT_SLL  (4)
 #define MX_VECT_SRL  (5)
-
 #define MX_VECT_ADD  (6)
 #define MX_VECT_SUB  (7)
 #define MX_VECT_MIN  (8)
@@ -751,6 +752,8 @@ typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 #define MX_VECT_MUL  (10)
 #define MX_VECT_MSGN (11)
 #define MX_VECT_SRA  (12)
+#define MX_VECT_ABSD (13)		/* SB-1 only.  */
+#define MX_VECT_AVG  (14)		/* SB-1 only.  */
 
 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
@@ -766,6 +769,8 @@ unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmt
 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
+#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
+#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
 
 #define MX_C_EQ  0x1
 #define MX_C_LT  0x4
@@ -784,6 +789,7 @@ unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fm
 #define MX_VECT_MULSL (5)
 #define MX_VECT_SUBA  (6)
 #define MX_VECT_SUBL  (7)
+#define MX_VECT_ABSDA (8)		/* SB-1 only.  */
 
 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
@@ -794,6 +800,7 @@ void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
+#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
 
 #define MX_FMT_OB   (0)
 #define MX_FMT_QH   (1)