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| author | Andrew Cagney <cagney@redhat.com> | 1998-04-02 19:35:39 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-04-02 19:35:39 +0000 |
| commit | 69d5a56645fdfd5d9cc9f57986224b0636010161 (patch) | |
| tree | d4ae76050ff337489375b4171bea76c1783243db /sim/mips/tx.igen | |
| parent | 7cdd6cac82faad2083029b2ac014d44d869f76c0 (diff) | |
| download | gdb-69d5a56645fdfd5d9cc9f57986224b0636010161.zip gdb-69d5a56645fdfd5d9cc9f57986224b0636010161.tar.gz gdb-69d5a56645fdfd5d9cc9f57986224b0636010161.tar.bz2 | |
Re-do load/store operations so that they work for both 32 and 64 bit
ISAs.
Enable tx39 as igen again.
Diffstat (limited to 'sim/mips/tx.igen')
| -rw-r--r-- | sim/mips/tx.igen | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/sim/mips/tx.igen b/sim/mips/tx.igen new file mode 100644 index 0000000..7e4af39 --- /dev/null +++ b/sim/mips/tx.igen @@ -0,0 +1,45 @@ +// -*- C -*- +// +// toshiba specific instructions. +// + +011100,5.RS,5.RT,5.RD,00000000000:MMINORM:::MADD +"madd r<RS>, r<RT>":RD == 0 +"madd r<RD>, r<RS>, r<RT>" +*r3900 +// start-sanitize-r5900 +*r5900: +// end-sanitize-r5900 +{ + signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((signed64) EXTEND32 (GPR[RT]) + * (signed64) EXTEND32 (GPR[RS]))); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + LO = EXTEND32 (prod); + HI = EXTEND32 (VH4_8 (prod)); + TRACE_ALU_RESULT2 (HI, LO); + if(RD != 0 ) + GPR[RD] = LO; +} + + +011100,5.RS,5.RT,5.RD,00000000001:MMINORM:::MADDU +"maddu r<RS>, r<RT>":RD == 0 +"maddu r<RD>, r<RS>, r<RT>" +*r3900 +// start-sanitize-r5900 +*r5900: +// end-sanitize-r5900 +{ + unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((unsigned64) VL4_8 (GPR[RS]) + * (unsigned64) VL4_8 (GPR[RT]))); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + LO = EXTEND32 (prod); + HI = EXTEND32 (VH4_8 (prod)); + TRACE_ALU_RESULT2 (HI, LO); + if(RD != 0) + GPR[RD] = LO; +} + + |