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authorFrank Ch. Eigler <fche@redhat.com>1998-04-05 16:40:03 +0000
committerFrank Ch. Eigler <fche@redhat.com>1998-04-05 16:40:03 +0000
commitebcfd86a2ee6c08419b951d8176febaf683e9726 (patch)
tree92f401845f64b64f89c24b7f80fa881ca601c9c0 /sim/mips/sky-pke.h
parentd61cc1d4b1bd12d088aef46e97d6f79cf6b3dfb1 (diff)
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* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF
masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
Diffstat (limited to 'sim/mips/sky-pke.h')
-rw-r--r--sim/mips/sky-pke.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/sim/mips/sky-pke.h b/sim/mips/sky-pke.h
index 4816ce6..2e44ed4 100644
--- a/sim/mips/sky-pke.h
+++ b/sim/mips/sky-pke.h
@@ -45,6 +45,9 @@ typedef unsigned_4 quadword[4];
#define VU1_MEM0_SRCADDR_START 0x21008000
#define VU1_MEM1_SRCADDR_START 0x2100C000
+#define VU0_CIA (VU0_REGISTER_WINDOW_START + VU_REG_CIA)
+#define VU1_CIA (VU1_REGISTER_WINDOW_START + VU_REG_CIA)
+
/* GPUIF STAT register */
#define GPUIF_REG_STAT_APATH_E 11
#define GPUIF_REG_STAT_APATH_B 10