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| author | Frank Ch. Eigler <fche@redhat.com> | 1998-04-05 16:40:03 +0000 |
|---|---|---|
| committer | Frank Ch. Eigler <fche@redhat.com> | 1998-04-05 16:40:03 +0000 |
| commit | ebcfd86a2ee6c08419b951d8176febaf683e9726 (patch) | |
| tree | 92f401845f64b64f89c24b7f80fa881ca601c9c0 /sim/mips/sky-pke.c | |
| parent | d61cc1d4b1bd12d088aef46e97d6f79cf6b3dfb1 (diff) | |
| download | gdb-ebcfd86a2ee6c08419b951d8176febaf683e9726.zip gdb-ebcfd86a2ee6c08419b951d8176febaf683e9726.tar.gz gdb-ebcfd86a2ee6c08419b951d8176febaf683e9726.tar.bz2 | |
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF
masking facility for PATH3 transfers.
[ChangeLog.sky]
Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com>
* sky-libvpe.c (exec-inst): Added "M" bit detection for upper
instruction.
* sky-pke.c (pke_check_stall): Added more assertions.
(pke_code_mskpath3): Use new GPUIF M3P control register.
* sky-pke.h (VU[01]_CIA): New macros that give VU CIA
pseudo-register addresses.
* sky-vu.h (vu_device, VectorUnitState): Merged structs.
(VectorUnitState.mflag): New field.
(VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers.
* sky-vu.c (vu0_busy): New function.
(vu0_q_busy): New function.
(vu0_macro_issue): New function.
(vu0_micro_interlock_released): New function.
(vu0_busy_in_{micro,macro}_mode): Deleted stubs.
(vu0_macro_hazard_check): Deleted stubs.
(vu_attach): Adapted code to merged device & state struct.
(read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register.
[ChangeLog]
start-sanitize-sky
Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (*): Adapt code to merged VU device & state structs.
(decode_coproc): Execute COP2 each macroinstruction without
pipelining, by stepping VU to completion state. Adapted to
read_vu_*_reg style of register access.
* mips.igen ([SL]QC2): Removed these COP2 instructions.
* r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
* sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
end-sanitize-sky
Diffstat (limited to 'sim/mips/sky-pke.c')
| -rw-r--r-- | sim/mips/sky-pke.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/sim/mips/sky-pke.c b/sim/mips/sky-pke.c index ce775bd..ce5c478 100644 --- a/sim/mips/sky-pke.c +++ b/sim/mips/sky-pke.c @@ -1089,16 +1089,19 @@ pke_check_stall(struct pke_device* me, enum pke_check_target what) } else if(what == chk_path1) /* VU -> GPUIF */ { + ASSERT(me->pke_number == 1); if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 1) any_stall = 1; } else if(what == chk_path2) /* PKE -> GPUIF */ { + ASSERT(me->pke_number == 1); if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 2) any_stall = 1; } else if(what == chk_path3) /* DMA -> GPUIF */ { + ASSERT(me->pke_number == 1); if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 3) any_stall = 1; } @@ -1243,12 +1246,12 @@ pke_code_mskpath3(struct pke_device* me, unsigned_4 pkecode) /* set appropriate bit */ if(BIT_MASK_GET(imm, PKE_REG_MSKPATH3_B, PKE_REG_MSKPATH3_E) != 0) - gif_mode = GIF_REG_MODE_M3R_MASK; + gif_mode = GIF_REG_STAT_M3P; else gif_mode = 0; - /* write register; patrickm code will look at M3R bit only */ - PKE_MEM_WRITE(me, GIF_REG_MODE, & gif_mode, 4); + /* write register to "read-only" register; gpuif code will look at M3P bit only */ + PKE_MEM_WRITE(me, GIF_REG_VIF_M3P, & gif_mode, 4); /* done */ pke_pc_advance(me, 1); |