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| author | Andrew Cagney <cagney@redhat.com> | 1998-03-03 05:39:49 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-03-03 05:39:49 +0000 |
| commit | ca6f76d13558a4ae3935f309db6d4540114b6a14 (patch) | |
| tree | ee1d95cf7cebcc52a8b7bd8d0f011c6420725d50 /sim/mips/sim-main.h | |
| parent | 3cdda79a7cf4730828844e8523e42373214423a4 (diff) | |
| download | gdb-ca6f76d13558a4ae3935f309db6d4540114b6a14.zip gdb-ca6f76d13558a4ae3935f309db6d4540114b6a14.tar.gz gdb-ca6f76d13558a4ae3935f309db6d4540114b6a14.tar.bz2 | |
Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't check
for overflow).
Pacify GCC.
Diffstat (limited to 'sim/mips/sim-main.h')
| -rw-r--r-- | sim/mips/sim-main.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index f9a9278..697d145 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -126,7 +126,7 @@ convert (SD, CPU, cia, rm, op, from, to) int bit = ((cc == 0) ? 23 : (24 + (cc)));\ FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\ } -#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0) +#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0) /* This should be the COC1 value at the start of the preceding instruction: */ |