* Makefile.in (SIM_OBJS): Add dsp.o.

(dsp.o): New dependency.
(IGEN_INCLUDE): Add dsp.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
mipsisa64*-*-*): Add dsp to sim_igen_machine.
* configure: Regenerate.
* mips.igen: Add dsp model and include dsp.igen.
(MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
because these instructions are extended in DSP ASE.
* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
adding 6 DSP accumulator registers and 1 DSP control register.
(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
DSPCR_CCOND_SMASK): New define.
(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
* dsp.c, dsp.igen: New files for MIPS DSP ASE.

1 files changed, 49 insertions, 1 deletions

diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 10ddbf2..76e6374 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -312,7 +312,7 @@ struct _sim_cpu {
    state. */
 
 #ifndef TM_MIPS_H
-#define LAST_EMBED_REGNUM (89)
+#define LAST_EMBED_REGNUM (96)
 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 
 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
@@ -349,6 +349,51 @@ struct _sim_cpu {
 #define DEPC	(REGISTERS[87])
 #define EPC	(REGISTERS[88])
 
+#define AC0LOIDX	(33)	/* Must be the same register as LO */
+#define AC0HIIDX	(34)	/* Must be the same register as HI */
+#define AC1LOIDX	(90)
+#define AC1HIIDX	(91)
+#define AC2LOIDX	(92)
+#define AC2HIIDX	(93)
+#define AC3LOIDX	(94)
+#define AC3HIIDX	(95)
+
+#define DSPLO(N)	(REGISTERS[DSPLO_REGNUM[N]])
+#define DSPHI(N)	(REGISTERS[DSPHI_REGNUM[N]])
+
+#define DSPCRIDX	(96)	/* DSP control register */
+#define DSPCR		(REGISTERS[DSPCRIDX])
+
+#define DSPCR_POS_SHIFT		(0)
+#define DSPCR_POS_MASK		(0x3f)
+#define DSPCR_POS_SMASK		(DSPCR_POS_MASK << DSPCR_POS_SHIFT)
+
+#define DSPCR_SCOUNT_SHIFT	(7)
+#define DSPCR_SCOUNT_MASK	(0x3f)
+#define DSPCR_SCOUNT_SMASK	(DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
+
+#define DSPCR_CARRY_SHIFT	(13)
+#define DSPCR_CARRY_MASK	(1)
+#define DSPCR_CARRY_SMASK	(DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
+#define DSPCR_CARRY		(1 << DSPCR_CARRY_SHIFT)
+
+#define DSPCR_EFI_SHIFT		(14)
+#define DSPCR_EFI_MASK		(1)
+#define DSPCR_EFI_SMASK		(DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
+#define DSPCR_EFI		(1 << DSPCR_EFI_MASK)
+
+#define DSPCR_OUFLAG_SHIFT	(16)
+#define DSPCR_OUFLAG_MASK	(0xff)
+#define DSPCR_OUFLAG_SMASK	(DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
+#define DSPCR_OUFLAG4		(1 << (DSPCR_OUFLAG_SHIFT + 4))
+#define DSPCR_OUFLAG5		(1 << (DSPCR_OUFLAG_SHIFT + 5))
+#define DSPCR_OUFLAG6		(1 << (DSPCR_OUFLAG_SHIFT + 6))
+#define DSPCR_OUFLAG7		(1 << (DSPCR_OUFLAG_SHIFT + 7))
+
+#define DSPCR_CCOND_SHIFT	(24)
+#define DSPCR_CCOND_MASK	(0xf)
+#define DSPCR_CCOND_SMASK	(DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
+
   /* All internal state modified by signal_exception() that may need to be
      rolled back for passing moment-of-exception image back to gdb. */
   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
@@ -933,6 +978,9 @@ INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, addres
 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 extern FILE *tracefh;
 
+extern int DSPLO_REGNUM[4];
+extern int DSPHI_REGNUM[4];
+
 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 extern SIM_CORE_SIGNAL_FN mips_core_signal;