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| author | Chris Demetriou <cgd@google.com> | 2002-06-03 22:30:52 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-06-03 22:30:52 +0000 |
| commit | e80fc1523d15f2ff344ab9ef6798765dab9ca0db (patch) | |
| tree | 874033c1785d2f5e88e00923f3933bb7b5c2510c /sim/mips/sim-main.c | |
| parent | bad673a9cb51c25370660c88887d0ad3b34b007b (diff) | |
| download | gdb-e80fc1523d15f2ff344ab9ef6798765dab9ca0db.zip gdb-e80fc1523d15f2ff344ab9ef6798765dab9ca0db.tar.gz gdb-e80fc1523d15f2ff344ab9ef6798765dab9ca0db.tar.bz2 | |
2002-06-03 Chris Demetriou <cgd@broadcom.com>
* cp1.c: fix formatting of switch case and default labels.
* interp.c: Likewise.
* sim-main.c: Likewise.
Diffstat (limited to 'sim/mips/sim-main.c')
| -rw-r--r-- | sim/mips/sim-main.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c index 7b3e6c6..edee498 100644 --- a/sim/mips/sim-main.c +++ b/sim/mips/sim-main.c @@ -163,35 +163,35 @@ load_memory (SIM_DESC SD, switch (AccessLength) { - case AccessLength_QUADWORD : + case AccessLength_QUADWORD: { unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr); value1 = VH8_16 (val); value = VL8_16 (val); break; } - case AccessLength_DOUBLEWORD : + case AccessLength_DOUBLEWORD: value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr); break; - case AccessLength_SEPTIBYTE : + case AccessLength_SEPTIBYTE: value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr); break; - case AccessLength_SEXTIBYTE : + case AccessLength_SEXTIBYTE: value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr); break; - case AccessLength_QUINTIBYTE : + case AccessLength_QUINTIBYTE: value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr); break; - case AccessLength_WORD : + case AccessLength_WORD: value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr); break; - case AccessLength_TRIPLEBYTE : + case AccessLength_TRIPLEBYTE: value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr); break; - case AccessLength_HALFWORD : + case AccessLength_HALFWORD: value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr); break; - case AccessLength_BYTE : + case AccessLength_BYTE: value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr); break; default: @@ -292,34 +292,34 @@ store_memory (SIM_DESC SD, switch (AccessLength) { - case AccessLength_QUADWORD : + case AccessLength_QUADWORD: { unsigned_16 val = U16_8 (MemElem1, MemElem); sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val); break; } - case AccessLength_DOUBLEWORD : + case AccessLength_DOUBLEWORD: sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_SEPTIBYTE : + case AccessLength_SEPTIBYTE: sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_SEXTIBYTE : + case AccessLength_SEXTIBYTE: sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_QUINTIBYTE : + case AccessLength_QUINTIBYTE: sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_WORD : + case AccessLength_WORD: sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_TRIPLEBYTE : + case AccessLength_TRIPLEBYTE: sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_HALFWORD : + case AccessLength_HALFWORD: sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_BYTE : + case AccessLength_BYTE: sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem); break; default: |