sim: mips: Add simulator support for mips32r6/mips64r6

2022-02-01  Ali Lown  <ali.lown@imgtec.com>
	    Andrew Bennett  <andrew.bennett@imgtec.com>
	    Dragan Mladjenovic  <dragan.mladjenovic@rt-rk.com>
	    Faraz Shahbazker  <fshahbazker@wavecomp.com>

sim/common/ChangeLog:
	* sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21,
	EXTEND26): New macros.

sim/mips/ChangeLog:
	* Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen.
	* configure: Regenerate.
	* configure.ac: Support mipsisa32r6 and mipsisa64r6.
	(sim_engine_run): Pick simulator model from processor specified
	in e_flags.
	* cp1.c (value_fpr): Handle fmt_dc32.
	(fp_unary, fp_binary): Zero initialize locals.
	(update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac,
	fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub):
	New functions.
	(sim_fpu_class_mips_mapping): New.
	* cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define.
	* interp.c (MIPSR6_P): New.
	(load_word): Allow unaligned memory access for MIPSR6.
	* micromips.igen (sc, scd): Adapt to new do_sc* helper signature.
	* mips.igen: Add *r6 models.
	(signal_if_cti, forbiddenslot32): New helpers.
	(delayslot32): Use signal_if_cti.
	(do_sc, do_scd); Add store_ll_bit parameter.
	(sc, scd): Adapt to previous change.
	(nal, beq, bal): New definitions for *r6.
	(sll): Split nop and ssnop cases into ...
	(nop, ssnop): New definitions.
	(loadstore_ea): Use the 32-bit compatibility adressing.
	(cache): Split logic into ...
	(do_cache): New helper.
	(check_fpu): Select IEEE 754-2008 mode for R6.
	(not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
	check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add,
	li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd,
	daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra,
	dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr,
	jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror,
	rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav,
	srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt,
	tltu, tne, xor, xori, check_fmt_p, do_load_double,
	do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT,
	cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1,
	dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT,
	mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT,
	sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f,
	bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp,
	tlbr, tlbwi, tlbwr): Enable on *r6 models.
	* mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu,
	dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr,
	wsbh): Likewise.
	* mips3264r6.igen: New file.
	* sim-main.h (FP_formats): Add fmt_dc32.
	(FORBIDDEN_SLOT): New macros.
	(simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines.
	(fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina,
	fp_maxa, fp_fmadd, fp_fmsub): New declarations.
	(R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA,
	MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping
	previous declarations.

sim/testsuite/mips/ChangeLog:
	* basic.exp: Add r6-*.s tests.
	(run_r6_removed_test): New function.
	(run_endian_tests): New function.
	* hilo-hazard-3.s: Skip for mips*r6.
	* r2-fpu.s: New test.
	* r6-64.s: New test.
	* r6-branch.s: New test.
	* r6-forbidden.s: New test.
	* r6-fpu.s: New test.
	* r6-llsc-dp.s: New test.
	* r6-llsc-wp.s: New test.
	* r6-removed.csv: New test.
	* r6-removed.s: New test.
	* r6.s: New test.
	* utils-r6.inc: New inc.

1 files changed, 30 insertions, 0 deletions

diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen
index e0b838c..a28d989 100644
--- a/sim/mips/mips3264r2.igen
+++ b/sim/mips/mips3264r2.igen
@@ -193,6 +193,7 @@
 011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT
 "dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
 *mips64r2:
+*mips64r6:
 {
   check_u64 (SD_, instruction_0);
   do_dext (SD_, RT, RS, LSB, SIZE);
@@ -201,6 +202,7 @@
 011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM
 "dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
 *mips64r2:
+*mips64r6:
 {
   check_u64 (SD_, instruction_0);
   do_dextm (SD_, RT, RS, LSB, SIZE);
@@ -209,6 +211,7 @@
 011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU
 "dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
 *mips64r2:
+*mips64r6:
 {
   check_u64 (SD_, instruction_0);
   do_dextu (SD_, RT, RS, LSB, SIZE);
@@ -219,7 +222,9 @@
 "di":RT == 0
 "di r<RT>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_di (SD_, RT);
 }
@@ -228,6 +233,7 @@
 011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS
 "dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
 *mips64r2:
+*mips64r6:
 {
   check_u64 (SD_, instruction_0);
   do_dins (SD_, RT, RS, LSB, MSB);
@@ -236,6 +242,7 @@
 011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM
 "dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
 *mips64r2:
+*mips64r6:
 {
   check_u64 (SD_, instruction_0);
   do_dinsm (SD_, RT, RS, LSB, MSB);
@@ -244,6 +251,7 @@
 011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU
 "dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
 *mips64r2:
+*mips64r6:
 {
   check_u64 (SD_, instruction_0);
   do_dinsu (SD_, RT, RS, LSB, MSB);
@@ -253,6 +261,7 @@
 011111,00000,5.RT,5.RD,00010,100100::64::DSBH
 "dsbh r<RD>, r<RT>"
 *mips64r2:
+*mips64r6:
 {
   check_u64 (SD_, instruction_0);
   do_dsbh (SD_, RD, RT);
@@ -261,6 +270,7 @@
 011111,00000,5.RT,5.RD,00101,100100::64::DSHD
 "dshd r<RD>, r<RT>"
 *mips64r2:
+*mips64r6:
 {
   check_u64 (SD_, instruction_0);
   do_dshd (SD_, RD, RT);
@@ -270,7 +280,9 @@
 "ei":RT == 0
 "ei r<RT>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_ei (SD_, RT);
 }
@@ -279,7 +291,9 @@
 011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT
 "ext r<RT>, r<RS>, <LSB>, <SIZE+1>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_ext (SD_, RT, RS, LSB, SIZE);
 }
@@ -288,7 +302,9 @@
 010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1
 "mfhc1 r<RT>, f<FS>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_mfhc1 (SD_, RT, FS);
 }
@@ -296,7 +312,9 @@
 010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1
 "mthc1 r<RT>, f<FS>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_mthc1 (SD_, RT, FS);
 }
@@ -305,7 +323,9 @@
 011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS
 "ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_ins (SD_, RT, RS, LSB, MSB);
 }
@@ -314,7 +334,9 @@
 011111,00000,5.RT,5.RD,10000,100000::32::SEB
 "seb r<RD>, r<RT>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_seb (SD_, RD, RT);
 }
@@ -322,7 +344,9 @@
 011111,00000,5.RT,5.RD,11000,100000::32::SEH
 "seh r<RD>, r<RT>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_seh (SD_, RD, RT);
 }
@@ -331,7 +355,9 @@
 000001,5.BASE,11111,16.OFFSET::32::SYNCI
 "synci <OFFSET>(r<BASE>)"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   // sync i-cache - nothing to do currently
 }
@@ -340,7 +366,9 @@
 011111,00000,5.RT,5.RD,00000,111011::32::RDHWR
 "rdhwr r<RT>, r<RD>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_rdhwr (SD_, RT, RD);
 }
@@ -349,7 +377,9 @@
 011111,00000,5.RT,5.RD,00010,100000::32::WSBH
 "wsbh r<RD>, r<RT>"
 *mips32r2:
+*mips32r6:
 *mips64r2:
+*mips64r6:
 {
   do_wsbh (SD_, RD, RT);
 }