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| author | Steve Ellcey <sje@cup.hp.com> | 2012-10-03 21:11:46 +0000 |
|---|---|---|
| committer | Steve Ellcey <sje@cup.hp.com> | 2012-10-03 21:11:46 +0000 |
| commit | 37cb8f8e706d41879dfae054e577b4efa5ec1e28 (patch) | |
| tree | 13ac05cc1826059ca54fdf2f8def8427b5516818 /sim/mips/mips3264r2.igen | |
| parent | cbf1fdc93bda5201e7752df0d599a45d1fe1a153 (diff) | |
| download | gdb-37cb8f8e706d41879dfae054e577b4efa5ec1e28.zip gdb-37cb8f8e706d41879dfae054e577b4efa5ec1e28.tar.gz gdb-37cb8f8e706d41879dfae054e577b4efa5ec1e28.tar.bz2 | |
2012-10-04 Chao-ying Fu <fu@mips.com>
Steve Ellcey <sellcey@mips.com>
* mips/mips3264r2.igen (rdhwr): New.
Diffstat (limited to 'sim/mips/mips3264r2.igen')
| -rw-r--r-- | sim/mips/mips3264r2.igen | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen index c52ec3b..e0b6d5b 100644 --- a/sim/mips/mips3264r2.igen +++ b/sim/mips/mips3264r2.igen @@ -241,6 +241,17 @@ } +011111,00000,5.RT,5.RD,00000,111011::32::RDHWR +"rdhwr r<RT>, r<RD>" +*mips32r2: +*mips64r2: +{ + // Return 0 for all hardware registers currently + GPR[RT] = EXTEND32 (0); + TRACE_ALU_RESULT1 (GPR[RT]); +} + + 011111,00000,5.RT,5.RD,00010,100000::32::WSBH "wsbh r<RD>, r<RT>" *mips32r2: |