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| author | Frank Ch. Eigler <fche@redhat.com> | 2000-03-02 18:14:02 +0000 |
|---|---|---|
| committer | Frank Ch. Eigler <fche@redhat.com> | 2000-03-02 18:14:02 +0000 |
| commit | a3027dd7480cbc4d681fa75bcd3ca2cabc6022a4 (patch) | |
| tree | cbd440a67d91151efdef83c66d9cd40d273bc040 /sim/mips/mips.igen | |
| parent | 58fddbac5a7cfd4404994be8d2a59dc8d72d7259 (diff) | |
| download | gdb-a3027dd7480cbc4d681fa75bcd3ca2cabc6022a4.zip gdb-a3027dd7480cbc4d681fa75bcd3ca2cabc6022a4.tar.gz gdb-a3027dd7480cbc4d681fa75bcd3ca2cabc6022a4.tar.bz2 | |
* autoconf correction
* merge from internal repo -> sourceware
2000-03-02 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated.
Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
calls, conditional on the simulator being in verbose mode.
Diffstat (limited to 'sim/mips/mips.igen')
| -rw-r--r-- | sim/mips/mips.igen | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 78998b0..3589b31 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -3031,7 +3031,13 @@ else if ((FS & 0x1) == 0) PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS])); else - PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%x: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n", + CIA); + PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); + } } } 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1 @@ -3055,7 +3061,12 @@ else if ((FS & 0x1) == 0) GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; else - GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%x: DMxC1 32-bit use of odd FPR number\n", CIA); + GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; + } } } @@ -3194,7 +3205,12 @@ if (X) { /*MTC1*/ if (SizeFGR() == 64) - PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT]))); + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%x: MTC1 not DMTC1 with 64 bit regs\n", CIA); + PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT]))); + } else PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT])); } |