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authorThiemo Seufer <ths@networkno.de>2006-08-29 12:45:26 +0000
committerThiemo Seufer <ths@networkno.de>2006-08-29 12:45:26 +0000
commit2d2733fc966f64220d26a99caf9ed4cb0c075f5d (patch)
tree97b3fa9d50e0953bb281d480f81391de9e4d32da /sim/mips/mips.igen
parentd85c3a10ae895627d2adb6f446bcf5017f7002d7 (diff)
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* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
sim_igen_machine. * configure: Regenerate. * mips.igen (model): Add smartmips. (MADDU): Increment ACX if carry. (do_mult): Clear ACX. (ROR,RORV): Add smartmips. (include): Include smartmips.igen. * sim-main.h (ACX): Set to REGISTERS[89]. * smartmips.igen: New file.
Diffstat (limited to 'sim/mips/mips.igen')
-rw-r--r--sim/mips/mips.igen6
1 files changed, 6 insertions, 0 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index e179cf0..85d08ea 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -72,6 +72,7 @@
:model:::mips3d:mips3d: // mips3d.igen
:model:::mdmx:mdmx: // mdmx.igen
:model:::dsp:dsp: // dsp.igen
+:model:::smartmips:smartmips: // smartmips.igen
// Vendor Extensions
//
@@ -2457,6 +2458,7 @@
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+ ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
@@ -2658,6 +2660,7 @@
* ((signed64)(signed32) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
+ ACX = 0; /* SmartMIPS */
if (rd != 0)
GPR[rd] = LO;
TRACE_ALU_RESULT2 (HI, LO);
@@ -2850,6 +2853,7 @@
"ror r<RD>, r<RT>, <SHIFT>"
*mips32r2:
*mips64r2:
+*smartmips:
*vr5400:
*vr5500:
{
@@ -2860,6 +2864,7 @@
"rorv r<RD>, r<RT>, r<RS>"
*mips32r2:
*mips64r2:
+*smartmips:
*vr5400:
*vr5500:
{
@@ -5683,4 +5688,5 @@
:include:::tx.igen
:include:::vr.igen
:include:::dsp.igen
+:include:::smartmips.igen