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| author | Frank Ch. Eigler <fche@redhat.com> | 1998-05-18 15:55:05 +0000 |
|---|---|---|
| committer | Frank Ch. Eigler <fche@redhat.com> | 1998-05-18 15:55:05 +0000 |
| commit | 3fa454e95fe104add1b25e53a8dc1decc1c270f1 (patch) | |
| tree | 9bb506f391e5eaece890333cda94a9a3f2e219af /sim/mips/mips.igen | |
| parent | d9c2c0c569da93bb393a078ebadbb89c1b6cca3b (diff) | |
| download | gdb-3fa454e95fe104add1b25e53a8dc1decc1c270f1.zip gdb-3fa454e95fe104add1b25e53a8dc1decc1c270f1.tar.gz gdb-3fa454e95fe104add1b25e53a8dc1decc1c270f1.tar.bz2 | |
* Monster patch - may destablize MIPS sims for a little while.
* Followup patch for SCEI PR 15853
* First check-in of TX3904 interrupt controller devices for ECC. [sanitized]
* First implementation of MIPS hardware interrupt emulation.
Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
modules. Recognize TX39 target with "mips*tx39" pattern.
* configure: Rebuilt.
* sim-main.h (*): Added many macros defining bits in
TX39 control registers.
(SignalInterrupt): Send actual PC instead of NULL.
(SignalNMIReset): New exception type.
* interp.c (board): New variable for future use to identify
a particular board being simulated.
(mips_option_handler,mips_options): Added "--board" option.
(interrupt_event): Send actual PC.
(sim_open): Make memory layout conditional on board setting.
(signal_exception): Initial implementation of hardware interrupt
handling. Accept another break instruction variant for simulator
exit.
(decode_coproc): Implement RFE instruction for TX39.
(mips.igen): Decode RFE instruction as such.
start-sanitize-tx3904
* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
* interp.c: Define "jmr3904" and "jmr3904debug" board types and
bbegin to implement memory map.
* dv-tx3904cpu.c: New file.
* dv-tx3904irc.c: New file.
end-sanitize-tx3904
Diffstat (limited to 'sim/mips/mips.igen')
| -rw-r--r-- | sim/mips/mips.igen | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 303de9d..a1f254c 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -124,6 +124,17 @@ } :function:::int:check_mt_hilo:hilo_history *history +*mipsI,mipsII,mipsIII,mipsIV: +*vr5000: +// start-sanitize-vr4320 +*vr4320: +// end-sanitize-vr4320 +// start-sanitize-vr5400 +*vr5400: +// end-sanitize-vr5400 +// start-sanitize-r5900 +*r5900: +// end-sanitize-r5900 { signed64 time = sim_events_time (SD); int ok = check_mf_cycles (SD_, history, time, "MT"); @@ -132,6 +143,18 @@ return ok; } +:function:::int:check_mt_hilo:hilo_history *history +*r3900: +// start-sanitize-tx19 +*tx19: +// end-sanitize-tx19 +{ + signed64 time = sim_events_time (SD); + history->mt.timestamp = time; + history->mt.cia = CIA; + return 1; +} + :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer { signed64 time = sim_events_time (SD); @@ -5351,6 +5374,7 @@ 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 "mfc0 r<RT>, r<RD> # <REGX>" *mipsI,mipsII,mipsIII,mipsIV: +*r3900: *vr5000: // start-sanitize-vr4320 *vr4320: @@ -5389,6 +5413,28 @@ } +010000,10000,000000000000000,010000:COP0:32::RFE +"rfe" +*mipsI,mipsII,mipsIII,mipsIV: +// start-sanitize-tx19 +*tx19: +// end-sanitize-tx19 +*r3900: +// start-sanitize-vr4320 +*vr4320: +// end-sanitize-vr4320 +*vr5000: +// start-sanitize-vr5400 +*vr5400: +// end-sanitize-vr5400 +// start-sanitize-r5900 +*r5900: +// end-sanitize-r5900 +{ + DecodeCoproc (instruction_0); +} + + 010000,10000,000000000000000,001000:COP0:32::TLBP "tlbp" *mipsI,mipsII,mipsIII,mipsIV: |