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| author | Chris Demetriou <cgd@google.com> | 2002-02-11 02:19:38 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-02-11 02:19:38 +0000 |
| commit | 20ae00985d69195b9f777f19fe0c113672ba2f1c (patch) | |
| tree | 836b968f222c6d25f0716e12b96131ef83a02cce /sim/mips/mips.igen | |
| parent | d426c6b07f24df631df0e290bf3034b61498aee5 (diff) | |
| download | gdb-20ae00985d69195b9f777f19fe0c113672ba2f1c.zip gdb-20ae00985d69195b9f777f19fe0c113672ba2f1c.tar.gz gdb-20ae00985d69195b9f777f19fe0c113672ba2f1c.tar.bz2 | |
2002-02-10 Chris Demetriou cgd@sibyte.com
* mips.igen (ADDI): Print immediate value.
(BREAK): Print code.
(DADDIU, DSRAV, DSRLV): Print correct instruction name.
(SLL): Print "nop" specially, and don't run the code
that does the shift for the "nop" case.
Diffstat (limited to 'sim/mips/mips.igen')
| -rw-r--r-- | sim/mips/mips.igen | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 03f783a..3ed8f62 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -245,7 +245,7 @@ 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI -"addi r<RT>, r<RS>, IMMEDIATE" +"addi r<RT>, r<RS>, <IMMEDIATE>" *mipsI,mipsII,mipsIII,mipsIV: *vr4100: *vr5000: @@ -668,7 +668,7 @@ 000000,20.CODE,001101:SPECIAL:32::BREAK -"break" +"break <CODE>" *mipsI,mipsII,mipsIII,mipsIV: *vr4100: *vr5000: @@ -747,7 +747,7 @@ } 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU -"daddu r<RT>, r<RS>, <IMMEDIATE>" +"daddiu r<RT>, r<RS>, <IMMEDIATE>" *mipsIII: *mipsIV: *vr4100: @@ -1113,7 +1113,7 @@ } 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV -"dsra32 r<RT>, r<RD>, r<RS>" +"dsrav r<RT>, r<RD>, r<RS>" *mipsIII: *mipsIV: *vr4100: @@ -1160,7 +1160,7 @@ 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV -"dsrl32 r<RD>, r<RT>, r<RS>" +"dsrlv r<RD>, r<RT>, r<RS>" *mipsIII: *mipsIV: *vr4100: @@ -2012,13 +2012,17 @@ } 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL +"nop":RD == 0 && RT == 0 && SHIFT == 0 "sll r<RD>, r<RT>, <SHIFT>" *mipsI,mipsII,mipsIII,mipsIV: *vr4100: *vr5000: *r3900: { - do_sll (SD_, RT, RD, SHIFT); + /* Skip shift for NOP, so that there won't be lots of extraneous + trace output. */ + if (RD != 0 || RT != 0 || SHIFT != 0) + do_sll (SD_, RT, RD, SHIFT); } |